低功耗条件和加法器使用通逻辑拓扑

Conference Proceedings. IEEE Canadian Conference on Electrical and Computer Engineering (Cat. No.98TH8341) Pub Date : 1998-05-24 DOI:10.1109/CCECE.1998.682537

D. Saleem, D. Al-Khalili

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引用次数: 2

摘要

对低功耗条件和加法器(CSA)进行了不同逻辑形式的分析。与其他拓扑结构相比，Pass逻辑拓扑实现提供低功耗延迟产品，并且占用较少的硅面积。采用0.5 /spl μ / CMOS技术，设计并制作了采用通逻辑和标准CMOS的两个版本的CSA测试芯片。测试结果表明，Pass Logic CSA可实现50%的节能。

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Low power conditional sum adder using pass logic topology

The Low Power Conditional Sum Adder (CSA) has been analyzed using various logic styles. Pass logic topology implementation offered low power delay product and occupied less silicon area compared to other topologies. A test chip for two versions of the CSA using pass logic and standard CMOS has been designed and fabricated using 0.5 /spl mu/ CMOS technology. Test results indicate that 50% power saving has been achieved in Pass Logic CSA.

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Conference Proceedings. IEEE Canadian Conference on Electrical and Computer Engineering (Cat. No.98TH8341)

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