Simulation Technique for Thermal Resistance in CMOS-SOI Power Amplifier Integrated Circuits

Thermal resistance is an important design parameter for high power ICs, particularly for power amplifiers. Although the buried oxide underneath FETs in CMOS ICs presents a barrier to heat flow, the interconnect metals and surrounding oxide provide additional paths for heat-sinking. This paper describes a straightforward technique to simulate the layout-dependent thermal resistance of a CMOS-SOI IC including the interconnect effects. The technique is an adaptation of the widely-used electromagnetic solver EMX by Integrand Software to heat flow. Simulation results show that in representative layouts the thermal resistance is reduced by a factor of 1.5x to 2x by the presence of interconnects. The benefit of vias through the buried oxide is highlighted.