Adam G. Kimura, Adam R. Waite, Jonathan Scholl, Glen D. Via
{"title":"应用失效分析工具和技术实现集成电路的信任和保证","authors":"Adam G. Kimura, Adam R. Waite, Jonathan Scholl, Glen D. Via","doi":"10.31399/asm.edfa.2021-1.p012","DOIUrl":null,"url":null,"abstract":"\n Traditional post-fabrication testing can reliably verify whether or not an IC is working correctly, but it cannot tell the difference between an authentic and counterfeit chip or recognize design changes made with malicious intent. This article presents an IC decomposition workflow, based on FA tools and techniques, that provides a quantifiable level of assurance for components in a zero trust environment.","PeriodicalId":431761,"journal":{"name":"EDFA Technical Articles","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2021-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Applied Failure Analysis Tools and Techniques Toward Integrated Circuit Trust and Assurance\",\"authors\":\"Adam G. Kimura, Adam R. Waite, Jonathan Scholl, Glen D. Via\",\"doi\":\"10.31399/asm.edfa.2021-1.p012\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"\\n Traditional post-fabrication testing can reliably verify whether or not an IC is working correctly, but it cannot tell the difference between an authentic and counterfeit chip or recognize design changes made with malicious intent. This article presents an IC decomposition workflow, based on FA tools and techniques, that provides a quantifiable level of assurance for components in a zero trust environment.\",\"PeriodicalId\":431761,\"journal\":{\"name\":\"EDFA Technical Articles\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-02-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"EDFA Technical Articles\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.31399/asm.edfa.2021-1.p012\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"EDFA Technical Articles","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.31399/asm.edfa.2021-1.p012","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Applied Failure Analysis Tools and Techniques Toward Integrated Circuit Trust and Assurance
Traditional post-fabrication testing can reliably verify whether or not an IC is working correctly, but it cannot tell the difference between an authentic and counterfeit chip or recognize design changes made with malicious intent. This article presents an IC decomposition workflow, based on FA tools and techniques, that provides a quantifiable level of assurance for components in a zero trust environment.