{"title":"A PA for MBOFDM-UWB and IR-UWB transmitters","authors":"Praveen Gunturi, D. Kotecki","doi":"10.1109/MWSCAS.2015.7282193","DOIUrl":null,"url":null,"abstract":"This paper describes the design of 4.2 to 5.9 GHz CMOS power amplifier (PA) for applications in ultra-wideband (UWB) commuincations. The PA operates in the linear region over the input range of -12 dBm and delivers an output power of 6 dBm. The post layout simulations indicate the power added efficiency (PAE) is more than 35% at 5 GHz frequency and more than 20% between 4.2 GHz and 5.9 GHz. The input matching is realized by resistive feedback and the output and the interstage matching are realized using source degeneration inductors. The input and output reflection coefficients are less than -5 dB over the frequency from 4.2 GHz to 5.9 GHz. The PA can also be used in IR UWB transmitters and provides energy efficiency of 11.3%. The total chip area is approximately 0.7mm2 including electrostatic discharge (ESD) protection. The design is implemented in 180nm CMOS technology.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2015.7282193","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper describes the design of 4.2 to 5.9 GHz CMOS power amplifier (PA) for applications in ultra-wideband (UWB) commuincations. The PA operates in the linear region over the input range of -12 dBm and delivers an output power of 6 dBm. The post layout simulations indicate the power added efficiency (PAE) is more than 35% at 5 GHz frequency and more than 20% between 4.2 GHz and 5.9 GHz. The input matching is realized by resistive feedback and the output and the interstage matching are realized using source degeneration inductors. The input and output reflection coefficients are less than -5 dB over the frequency from 4.2 GHz to 5.9 GHz. The PA can also be used in IR UWB transmitters and provides energy efficiency of 11.3%. The total chip area is approximately 0.7mm2 including electrostatic discharge (ESD) protection. The design is implemented in 180nm CMOS technology.