Yongming Li, Hongyi Chen, Zhengdong Yu, Tong Chu, Kun Bian
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引用次数: 0
摘要
本文提出了一种能在单指令周期内完成Mbit/spl次/Nbit乘法运算的ALU设计。给出了该ALU的结构、操作控制和逻辑。给出了逻辑和spice(采用2 /spl μ m CMOS技术)的仿真结果。它可用于微处理器和微控制器，以提高它们的计算能力。
An ALU design which can perform Mbit/spl times/Nbit multiplication within single instruction period is presented in this paper. The architecture, operation control and logic for this ALU are given. Logical and spice (with 2 /spl mu/m CMOS technology) simulation results are also given. It can be used in MPUs and MCUs to enhance their computation capability.
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