T. Hiyama, Yuko Ito, S. Isomura, Kazunobu Nojiri, Eijiro Maeda
{"title":"千兆赫时代及以后逻辑lsi的先进布线RC时序设计技术","authors":"T. Hiyama, Yuko Ito, S. Isomura, Kazunobu Nojiri, Eijiro Maeda","doi":"10.1109/ICCD.2000.878340","DOIUrl":null,"url":null,"abstract":"In this paper, we describe an advanced wiring RC timing design techniques for the gigahertz era. Our new technique of wiring capacitance extraction makes it possible to calculate more than 1 M nets within 3 hours as accurately as carrying out net-by-net 3-D simulations. Furthermore, we introduced the timing window for estimating crosstalk effects on delay time so as to distinguish harmful nets from harmless nets and reduce surplus design guard-bands.","PeriodicalId":437697,"journal":{"name":"Proceedings 2000 International Conference on Computer Design","volume":"248 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Advanced wiring RC timing design techniques for logic LSIs in gigahertz era and beyond\",\"authors\":\"T. Hiyama, Yuko Ito, S. Isomura, Kazunobu Nojiri, Eijiro Maeda\",\"doi\":\"10.1109/ICCD.2000.878340\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we describe an advanced wiring RC timing design techniques for the gigahertz era. Our new technique of wiring capacitance extraction makes it possible to calculate more than 1 M nets within 3 hours as accurately as carrying out net-by-net 3-D simulations. Furthermore, we introduced the timing window for estimating crosstalk effects on delay time so as to distinguish harmful nets from harmless nets and reduce surplus design guard-bands.\",\"PeriodicalId\":437697,\"journal\":{\"name\":\"Proceedings 2000 International Conference on Computer Design\",\"volume\":\"248 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-09-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 2000 International Conference on Computer Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCD.2000.878340\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 2000 International Conference on Computer Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCD.2000.878340","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Advanced wiring RC timing design techniques for logic LSIs in gigahertz era and beyond
In this paper, we describe an advanced wiring RC timing design techniques for the gigahertz era. Our new technique of wiring capacitance extraction makes it possible to calculate more than 1 M nets within 3 hours as accurately as carrying out net-by-net 3-D simulations. Furthermore, we introduced the timing window for estimating crosstalk effects on delay time so as to distinguish harmful nets from harmless nets and reduce surplus design guard-bands.