{"title":"tft的人工神经网络压缩模型","authors":"Q. Chen, G. Chen","doi":"10.1109/CAD-TFT.2016.7785057","DOIUrl":null,"url":null,"abstract":"This paper reports a TFT compact modeling methodology based on artificial neural networks (ANNs). Both drain current and gate capacitance are modeled with good accuracy. Extendability to different W/L ratios is also tested.","PeriodicalId":303429,"journal":{"name":"2016 7th International Conference on Computer Aided Design for Thin-Film Transistor Technologies (CAD-TFT)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Artificial neural network compact model for TFTs\",\"authors\":\"Q. Chen, G. Chen\",\"doi\":\"10.1109/CAD-TFT.2016.7785057\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper reports a TFT compact modeling methodology based on artificial neural networks (ANNs). Both drain current and gate capacitance are modeled with good accuracy. Extendability to different W/L ratios is also tested.\",\"PeriodicalId\":303429,\"journal\":{\"name\":\"2016 7th International Conference on Computer Aided Design for Thin-Film Transistor Technologies (CAD-TFT)\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 7th International Conference on Computer Aided Design for Thin-Film Transistor Technologies (CAD-TFT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CAD-TFT.2016.7785057\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 7th International Conference on Computer Aided Design for Thin-Film Transistor Technologies (CAD-TFT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CAD-TFT.2016.7785057","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper reports a TFT compact modeling methodology based on artificial neural networks (ANNs). Both drain current and gate capacitance are modeled with good accuracy. Extendability to different W/L ratios is also tested.