A novel approach of test and fault isolation of high speed digital circuit modules

Along with the development of digitization and intelligentization for radar and other electronic equipment, high speed digital circuit (HSDC) modules involving CPU, DSP, FPGA and etc. are widely used in these electronic equipment. The highest bit rate of the HSDC modules can reach several Gbit/s or even higher, external interface for these modules adopt high speed interfaces such as RapidIO 2.0, PCI Express 2.0, 10G Ethernet and etc. The chips used by the module are usually packaged by BGA. The pins are hidden below the chip, so they are difficult to be tested by the test probe. The application of the new technology brings a great challenge to the test and the fault isolation of the HSDC module. The automatic test system(ATS) which is based on the traditional I/O module cannot meet the test requirements of the HSDC modules. This article analyses the test requirements of the HSDC module based on VPX bus, including : a) The requirement of generating high speed digital signal of multiple channels; b) The requirement of collecting high speed digital signal of multiple channels; c) The requirement of high speed adapter. This article proposes the HSDC module test system's architecture which is based on the VPX bus. It introduces the function and specifications of the key components in this test system's architecture. The key components consist of high speed digital IO module, high speed interface module and high speed digital signal interface's adapter. High speed digital IO module is used to generate and collect the signal of RapidIO, RocketIO and other high speed digital signal. High speed interface module is used for the interface of the high speed optical fiber signal and the high speed ethernet signal. The high speed digital signal interface's adapter is used for connection between high speed digital test modules and UUT. The article also brings forward the fault isolation method of HSDC module of combining boundary scan and embedded test. Boundary scan is used for isolating open circuit fault and short circuit fault of HSDC modules. Test probe is not required by this method. The embedded test includes the method based on the test IP kernel and the method based on module BIT. Utilizing the method based on the test IP kernel, we can test the signal on internal test point of FPGA and pins of other chips (e.g., RAM, DSP). Utilizing the method based on module BIT, the chips fault and interface fault can be detected. It introduces the difference between the HSDC module and the traditional digital circuit module in the development of test program. The test and diagnosis methods presented in this article have already been used in several kinds of HSDC module.