A Low Complexity DDS Based On Optimized CORDIC Algorithm

Aiming at the high-speed and low complexity of Direct Digital Frequency Synthesizer (DDS), this paper presents an improved structure of CORDIC algorithm (the excess-four algorithm). The mathematical approximate calculation is used to optimize the circuit structure of the rotating module in the excess-four algorithm, which reduces the adder in the rotating module and the hardware consumption of the circuit effectively. By removing the carry-over operation of the phase accumulating module, all the three-level rotating modules have the same structure, which ensures the same delay in all rotating units. The approach makes more advantages in the design of high-speed DDS circuits. Using the improved rotating structure, this paper implements the design of a highspeed DDS digital unit up to 6Gsps, with the SFDR above 88dBc, up to 104dBc. The single DDS core area is approximately 0.14 mm2 and the power consumption is 0.01mW/ MHz, using the Synopsys' SMIC 65nm process library tool to complete ASIC back-end design. In the case of SFDR that meets most of the high-speed DDS digital parts, the area and power consumption in this paper are greatly improved, compared with the conventional implementation method.