{"title":"超过10nm FinFET技术的SRAM电池性能分析","authors":"M. Ichihashi, Y. Woo, S. Parihar","doi":"10.1109/VLSI-TSA.2016.7480512","DOIUrl":null,"url":null,"abstract":"This paper describes the performance analysis of SRAM cell capability beyond 10-nm FinFET technology. Through the circuit simulation with a pseudo memory macro, optimized SRAM cell can demonstrate almost the same performance of traditional metal architecture though the read-out delay analysis. Comparing between HD (High-Density) and HC (High-Current) cell, HD cell shows better performance in the large array macro due to the less parasitic resistance and capacitance.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"SRAM cell performance analysis beyond 10-nm FinFET technology\",\"authors\":\"M. Ichihashi, Y. Woo, S. Parihar\",\"doi\":\"10.1109/VLSI-TSA.2016.7480512\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes the performance analysis of SRAM cell capability beyond 10-nm FinFET technology. Through the circuit simulation with a pseudo memory macro, optimized SRAM cell can demonstrate almost the same performance of traditional metal architecture though the read-out delay analysis. Comparing between HD (High-Density) and HC (High-Current) cell, HD cell shows better performance in the large array macro due to the less parasitic resistance and capacitance.\",\"PeriodicalId\":441941,\"journal\":{\"name\":\"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)\",\"volume\":\"120 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-04-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSI-TSA.2016.7480512\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-TSA.2016.7480512","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper describes the performance analysis of SRAM cell capability beyond 10-nm FinFET technology. Through the circuit simulation with a pseudo memory macro, optimized SRAM cell can demonstrate almost the same performance of traditional metal architecture though the read-out delay analysis. Comparing between HD (High-Density) and HC (High-Current) cell, HD cell shows better performance in the large array macro due to the less parasitic resistance and capacitance.