温度效应表征的Mosfet亚微米模型

H. Masuda, R. Ikematsu, J. Mano, H. Sugihara
{"title":"温度效应表征的Mosfet亚微米模型","authors":"H. Masuda, R. Ikematsu, J. Mano, H. Sugihara","doi":"10.1109/NUPAD.1990.748282","DOIUrl":null,"url":null,"abstract":"This paper presents a new circuit model for sub-um NMOSFETs and describes experiments on them. The model is focused on the temperature effect on I-V and CV characteristics. The resulting I-V modeling error (RMS: Root Mean Square) is verified to be less than 1.5% for Vd=O-SV and Vg=O-SV operating conditions, and 300-450K temperature range. The CV model error also examined, showing 6.0% at 400K. Drain current characteristics were measured with a 0.8um NMOS under various temperature conditions. Through experiments and parameter extraction (for MOSTSM model[ 1][2]) on the measured I-V data, the following results are noted (see Fig. 1). (1) Channel conductance of a unit area (Po) exhibits a significant decrease (one half) for the temperature rise from 300K to 450K. However, the corresponding drain current reduction is only 20% at Vds=Vgs=SV. (2) The above effect is caused by a change in the gate-field effect factor of channelconductance (eel ), which shows a monotonic decrease for rising temperature [4]. MOST temperature model","PeriodicalId":348970,"journal":{"name":"Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Mosfet Submicron Model For Temperature Effect Characterization\",\"authors\":\"H. Masuda, R. Ikematsu, J. Mano, H. Sugihara\",\"doi\":\"10.1109/NUPAD.1990.748282\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a new circuit model for sub-um NMOSFETs and describes experiments on them. The model is focused on the temperature effect on I-V and CV characteristics. The resulting I-V modeling error (RMS: Root Mean Square) is verified to be less than 1.5% for Vd=O-SV and Vg=O-SV operating conditions, and 300-450K temperature range. The CV model error also examined, showing 6.0% at 400K. Drain current characteristics were measured with a 0.8um NMOS under various temperature conditions. Through experiments and parameter extraction (for MOSTSM model[ 1][2]) on the measured I-V data, the following results are noted (see Fig. 1). (1) Channel conductance of a unit area (Po) exhibits a significant decrease (one half) for the temperature rise from 300K to 450K. However, the corresponding drain current reduction is only 20% at Vds=Vgs=SV. (2) The above effect is caused by a change in the gate-field effect factor of channelconductance (eel ), which shows a monotonic decrease for rising temperature [4]. MOST temperature model\",\"PeriodicalId\":348970,\"journal\":{\"name\":\"Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-06-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NUPAD.1990.748282\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NUPAD.1990.748282","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

本文提出了一种新的亚微米nmosfet电路模型,并对其进行了实验。该模型的重点是温度对I-V和CV特性的影响。在Vd=O-SV和Vg=O-SV工况下,以及300-450K温度范围内,由此产生的I-V建模误差(RMS:均方根)小于1.5%。还检查了CV模型误差,在400K时显示6.0%。用0.8um NMOS测量了不同温度条件下的漏极电流特性。通过对实测I-V数据进行实验和参数提取(对于MOSTSM模型[1][2]),得到如下结果(见图1):(1)从300K到450K温度升高,单位面积沟道电导(Po)显著减小(一半)。然而,在Vds=Vgs=SV时,相应的漏极电流减少仅为20%。(2)上述效应是由通道电导门场效应因子(eel)的变化引起的,随着温度的升高,通道电导门场效应因子呈单调下降趋势。MOST温度模型
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Mosfet Submicron Model For Temperature Effect Characterization
This paper presents a new circuit model for sub-um NMOSFETs and describes experiments on them. The model is focused on the temperature effect on I-V and CV characteristics. The resulting I-V modeling error (RMS: Root Mean Square) is verified to be less than 1.5% for Vd=O-SV and Vg=O-SV operating conditions, and 300-450K temperature range. The CV model error also examined, showing 6.0% at 400K. Drain current characteristics were measured with a 0.8um NMOS under various temperature conditions. Through experiments and parameter extraction (for MOSTSM model[ 1][2]) on the measured I-V data, the following results are noted (see Fig. 1). (1) Channel conductance of a unit area (Po) exhibits a significant decrease (one half) for the temperature rise from 300K to 450K. However, the corresponding drain current reduction is only 20% at Vds=Vgs=SV. (2) The above effect is caused by a change in the gate-field effect factor of channelconductance (eel ), which shows a monotonic decrease for rising temperature [4]. MOST temperature model
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信