通过在铝电线上平面化介电膜来增加电磁电阻

Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference Pub Date : 1989-06-12 DOI:10.1109/VMIC.1989.78019

A. Isobe, Y. Numazawa, M. Sakamoto

{"title":"通过在铝电线上平面化介电膜来增加电磁电阻","authors":"A. Isobe, Y. Numazawa, M. Sakamoto","doi":"10.1109/VMIC.1989.78019","DOIUrl":null,"url":null,"abstract":"The relation between EM (electromigration) characteristics and interlayer dielectric film structure is described. It was found that a well-planarized interlayer significantly increases EM resistance for underlying Al wirings. This EM improvement is attributed to reinforcement and crack suppression at interlayer sidewalls. A constant atom flux model is proposed that explains the mechanism for this phenomenon.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Increase in EM resistance by planarizing dielectric film over Al wirings\",\"authors\":\"A. Isobe, Y. Numazawa, M. Sakamoto\",\"doi\":\"10.1109/VMIC.1989.78019\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The relation between EM (electromigration) characteristics and interlayer dielectric film structure is described. It was found that a well-planarized interlayer significantly increases EM resistance for underlying Al wirings. This EM improvement is attributed to reinforcement and crack suppression at interlayer sidewalls. A constant atom flux model is proposed that explains the mechanism for this phenomenon.<<ETX>>\",\"PeriodicalId\":302853,\"journal\":{\"name\":\"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VMIC.1989.78019\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VMIC.1989.78019","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

描述了电迁移特性与层间介质膜结构之间的关系。研究发现，平面化良好的中间层显著增加了底层铝线的电磁电阻。这种EM的改善归功于层间侧壁的加固和裂纹抑制。提出了一个常数原子通量模型来解释这一现象的机理。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Increase in EM resistance by planarizing dielectric film over Al wirings

The relation between EM (electromigration) characteristics and interlayer dielectric film structure is described. It was found that a well-planarized interlayer significantly increases EM resistance for underlying Al wirings. This EM improvement is attributed to reinforcement and crack suppression at interlayer sidewalls. A constant atom flux model is proposed that explains the mechanism for this phenomenon.<>

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference

自引率

0.00%

发文量