断路和短路故障电阻对MCML栅极生产试验的影响

R. M. El-Din, A. S. Emara, S. Amer, M. M. Fouad, A. Madian, H. Amer, M. B. Abdelhalim, H. H. Draz
{"title":"断路和短路故障电阻对MCML栅极生产试验的影响","authors":"R. M. El-Din, A. S. Emara, S. Amer, M. M. Fouad, A. Madian, H. Amer, M. B. Abdelhalim, H. H. Draz","doi":"10.1109/BEC.2014.7320561","DOIUrl":null,"url":null,"abstract":"This paper focuses on the production testing of MOS Current Mode Logic (MCML) gates based on 45nm MOS technology. The effect of the resistance value of open faults in an NAND/AND gate is investigated. It is shown that the test speed is determined by the characteristics of the pull up load. Open faults in other transistors are not affected by test speed. Also, it is proven that only three ordered test vectors are needed to detect all open as well as short resistive faults in the gate. Finally, the effect of the resistance of short faults is studied and it is found that the value of the resistance of the short does not affect the ability of vectors to detect faults in the 45nm technology while this is not the case for the 90nm MCML or the 45nm CMOS technologies.","PeriodicalId":348260,"journal":{"name":"2014 14th Biennial Baltic Electronic Conference (BEC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Effect of the resistance of open and short faults on the production testing of MCML gates\",\"authors\":\"R. M. El-Din, A. S. Emara, S. Amer, M. M. Fouad, A. Madian, H. Amer, M. B. Abdelhalim, H. H. Draz\",\"doi\":\"10.1109/BEC.2014.7320561\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper focuses on the production testing of MOS Current Mode Logic (MCML) gates based on 45nm MOS technology. The effect of the resistance value of open faults in an NAND/AND gate is investigated. It is shown that the test speed is determined by the characteristics of the pull up load. Open faults in other transistors are not affected by test speed. Also, it is proven that only three ordered test vectors are needed to detect all open as well as short resistive faults in the gate. Finally, the effect of the resistance of short faults is studied and it is found that the value of the resistance of the short does not affect the ability of vectors to detect faults in the 45nm technology while this is not the case for the 90nm MCML or the 45nm CMOS technologies.\",\"PeriodicalId\":348260,\"journal\":{\"name\":\"2014 14th Biennial Baltic Electronic Conference (BEC)\",\"volume\":\"48 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 14th Biennial Baltic Electronic Conference (BEC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BEC.2014.7320561\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 14th Biennial Baltic Electronic Conference (BEC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BEC.2014.7320561","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

本文重点研究了基于45纳米MOS技术的MOS电流模式逻辑(MCML)门的量产测试。研究了非与与栅极中开路故障电阻值的影响。结果表明,试验速度是由上拉载荷的特性决定的。其它晶体管的开路故障不受测试速度的影响。此外,还证明了仅需要三个有序的测试向量就可以检测栅极中的所有开路故障和短电阻故障。最后,研究了短故障电阻的影响,发现在45nm技术中,短电阻的值不影响矢量检测故障的能力,而在90nm MCML或45nm CMOS技术中则不是这样。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Effect of the resistance of open and short faults on the production testing of MCML gates
This paper focuses on the production testing of MOS Current Mode Logic (MCML) gates based on 45nm MOS technology. The effect of the resistance value of open faults in an NAND/AND gate is investigated. It is shown that the test speed is determined by the characteristics of the pull up load. Open faults in other transistors are not affected by test speed. Also, it is proven that only three ordered test vectors are needed to detect all open as well as short resistive faults in the gate. Finally, the effect of the resistance of short faults is studied and it is found that the value of the resistance of the short does not affect the ability of vectors to detect faults in the 45nm technology while this is not the case for the 90nm MCML or the 45nm CMOS technologies.
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