A novel high integration-density TFT-CMOS inverter with vertical structure for low power application

In this paper, a novel vertical-like TFT-CMOS inverter with simple process and high integration density is proposed, which is composed of a pseudo-planar CMOS. Two compared devices are also designed for comparison, namely, the vertical complementary metal-oxide-semiconductor (VCMOS) and planar complementary metal-oxide-semiconductor (PCMOS). According to simulation results, the source overlap region is used to obtain a high drain saturation current, the drain underlap region is used to obtain a low Ioff, and the BOI is used to reduce the drain off-state current. we find out that the proposed approach achieves a 59.5% area reduction and significant shortening of wiring distance between the active devices when compared with existing planar CMOS technology.