Low power multiplier design using adiabatic SCRL logic

Since, the scale of the integration keeps on growing more and more signal processing applications need to be implemented on the Very Large Scale Integrated chip. These applications demand great computational capacity along with a considerable amount of energy. The objective of this paper is to provide promising low power solution for multiplier design for Very Large Scale Integration. The focus is on the reduction of power dissipation which is showing an ever-increasing growth with the scaling down of the techniques. The paper primarily throws light on low power multiplier design using Radix-4 modified booth's algorithm using Split Charge Recovery Logic. In standard Complementary Metal Oxide Semiconductor Circuits, bits are discarded after every transformation in the output level. As a result of which, the energy becomes heat, which in turn increases overhead needed to get rid of heat causing battery life problem. Modified booth's algorithm using Split Charge Recovery Logic circuit offers an efficient way to get out of this problem. A low power Multiplier is designed using modified booth's algorithm using Split Charge Recovery Logic. In the future, various different circuits can be implemented using adiabatic low power design.