基于平台的设计框架,促进多核心软件开发

G. Madalozzo, Marcelo G. Mandelli, Luciano Ost, F. Moraes
{"title":"基于平台的设计框架,促进多核心软件开发","authors":"G. Madalozzo, Marcelo G. Mandelli, Luciano Ost, F. Moraes","doi":"10.1109/ICECS.2015.7440313","DOIUrl":null,"url":null,"abstract":"Embedded software engineers are dealing with complex and large software codes, which will continue to grow. To achieve a cost-effective design, concomitant hardware and software development is required during early design phases. This paper presents an open-source platform based design framework that combines different ADLs and simulators aiming at improving embedded software productivity, targeting future many-core embedded systems. The proposed approach adopts three models: RTL-VHDL level; RTL-SystemC coupled to ISSs; PBD (Platform Based Design) using OVP. The software (operating system and user applications) is the same for both models. Therefore, the OVP modeling allows fast software validation and debuggability. With the SystemC-ISS, it is possible to accurate estimate performance and energy consumption. The low-level model enables, besides area estimation, the validation of low-level protocols, as the communication protocol, network interface or flow-control mechanisms between routers. Results evaluate execution time, simulation time, and the number of executed instructions for several benchmarks using the proposed approach. The OVP model presents in average five times faster than the RTL-SystemC model, and the RTL-SystemC up to 155 times faster than the RTL-VHDL model.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A platform-based design framework to boost many-core software development\",\"authors\":\"G. Madalozzo, Marcelo G. Mandelli, Luciano Ost, F. Moraes\",\"doi\":\"10.1109/ICECS.2015.7440313\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Embedded software engineers are dealing with complex and large software codes, which will continue to grow. To achieve a cost-effective design, concomitant hardware and software development is required during early design phases. This paper presents an open-source platform based design framework that combines different ADLs and simulators aiming at improving embedded software productivity, targeting future many-core embedded systems. The proposed approach adopts three models: RTL-VHDL level; RTL-SystemC coupled to ISSs; PBD (Platform Based Design) using OVP. The software (operating system and user applications) is the same for both models. Therefore, the OVP modeling allows fast software validation and debuggability. With the SystemC-ISS, it is possible to accurate estimate performance and energy consumption. The low-level model enables, besides area estimation, the validation of low-level protocols, as the communication protocol, network interface or flow-control mechanisms between routers. Results evaluate execution time, simulation time, and the number of executed instructions for several benchmarks using the proposed approach. The OVP model presents in average five times faster than the RTL-SystemC model, and the RTL-SystemC up to 155 times faster than the RTL-VHDL model.\",\"PeriodicalId\":215448,\"journal\":{\"name\":\"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)\",\"volume\":\"21 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-12-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.2015.7440313\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2015.7440313","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

嵌入式软件工程师正在处理复杂和大型的软件代码,这些代码将继续增长。为了实现具有成本效益的设计,在早期设计阶段需要同时进行硬件和软件开发。本文提出了一个基于开源平台的设计框架,该框架结合了不同的adl和模拟器,旨在提高嵌入式软件的生产力,面向未来的多核嵌入式系统。该方法采用三种模型:RTL-VHDL级;RTL-SystemC与iss耦合;PBD(基于平台的设计)使用OVP。两种型号的软件(操作系统和用户应用程序)是相同的。因此,OVP建模允许快速的软件验证和可调试性。使用SystemC-ISS,可以准确估计性能和能耗。除了面积估计之外,低级模型还可以验证低级协议,如路由器之间的通信协议、网络接口或流量控制机制。结果评估了使用所建议的方法的几个基准测试的执行时间、模拟时间和执行指令的数量。OVP模型比RTL-SystemC模型平均快5倍,RTL-SystemC模型比RTL-VHDL模型快155倍。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A platform-based design framework to boost many-core software development
Embedded software engineers are dealing with complex and large software codes, which will continue to grow. To achieve a cost-effective design, concomitant hardware and software development is required during early design phases. This paper presents an open-source platform based design framework that combines different ADLs and simulators aiming at improving embedded software productivity, targeting future many-core embedded systems. The proposed approach adopts three models: RTL-VHDL level; RTL-SystemC coupled to ISSs; PBD (Platform Based Design) using OVP. The software (operating system and user applications) is the same for both models. Therefore, the OVP modeling allows fast software validation and debuggability. With the SystemC-ISS, it is possible to accurate estimate performance and energy consumption. The low-level model enables, besides area estimation, the validation of low-level protocols, as the communication protocol, network interface or flow-control mechanisms between routers. Results evaluate execution time, simulation time, and the number of executed instructions for several benchmarks using the proposed approach. The OVP model presents in average five times faster than the RTL-SystemC model, and the RTL-SystemC up to 155 times faster than the RTL-VHDL model.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信