{"title":"采用1.15ps SAR-TDC的79dB SNDR, 10MHz BW, 675MS/s开环基于时间的ADC","authors":"W. El-Halwagy, P. Mousavi, Masum Hossain","doi":"10.1109/ASSCC.2016.7844200","DOIUrl":null,"url":null,"abstract":"This paper introduces a first-order noise-shaped time-domain ADC utilizing SAR-TDC as quantizer. The high resolution correlated double sampling SAR-TDC improves the quantization noise level of the ADC. The VCO non-linearity is resolved by employing a 1-bit folded VCO architecture. The ADC linearity is further improved using foreground digital calibration. Implemented in 65nm CMOS, the 675MS/s time-domain ADC achieves measured peak SNDR/SFDR of 79.5/86.4dB in 10MHz BW while consuming 11.65mW. The SAR-TDC achieves 1.15ps resolution with peak measured DNL/INL of 0.64/0.65LSB. The 1-bit folded VCO improves the VCO linearity from 12% to 0.17%.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"A 79dB SNDR, 10MHz BW, 675MS/s open-loop time-based ADC employing a 1.15ps SAR-TDC\",\"authors\":\"W. El-Halwagy, P. Mousavi, Masum Hossain\",\"doi\":\"10.1109/ASSCC.2016.7844200\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper introduces a first-order noise-shaped time-domain ADC utilizing SAR-TDC as quantizer. The high resolution correlated double sampling SAR-TDC improves the quantization noise level of the ADC. The VCO non-linearity is resolved by employing a 1-bit folded VCO architecture. The ADC linearity is further improved using foreground digital calibration. Implemented in 65nm CMOS, the 675MS/s time-domain ADC achieves measured peak SNDR/SFDR of 79.5/86.4dB in 10MHz BW while consuming 11.65mW. The SAR-TDC achieves 1.15ps resolution with peak measured DNL/INL of 0.64/0.65LSB. The 1-bit folded VCO improves the VCO linearity from 12% to 0.17%.\",\"PeriodicalId\":278002,\"journal\":{\"name\":\"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)\",\"volume\":\"44 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2016.7844200\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2016.7844200","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 79dB SNDR, 10MHz BW, 675MS/s open-loop time-based ADC employing a 1.15ps SAR-TDC
This paper introduces a first-order noise-shaped time-domain ADC utilizing SAR-TDC as quantizer. The high resolution correlated double sampling SAR-TDC improves the quantization noise level of the ADC. The VCO non-linearity is resolved by employing a 1-bit folded VCO architecture. The ADC linearity is further improved using foreground digital calibration. Implemented in 65nm CMOS, the 675MS/s time-domain ADC achieves measured peak SNDR/SFDR of 79.5/86.4dB in 10MHz BW while consuming 11.65mW. The SAR-TDC achieves 1.15ps resolution with peak measured DNL/INL of 0.64/0.65LSB. The 1-bit folded VCO improves the VCO linearity from 12% to 0.17%.
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