{"title":"IBM ES/9000系统架构和硬件","authors":"W. J. Nohilly, V. Lund","doi":"10.1109/ICCD.1991.139968","DOIUrl":null,"url":null,"abstract":"A description is given how IBM's Enterprise Systems requirements for data management are implemented in the ES/9000 process series. The ES/9000 processor family is the next step in efficient data movement/management for data that reside anywhere in the Enterprise. To manage this vast amount of data, certain high end ES/9000 models utilize four levels of memory (L1 or first level cache, L2 or second level buffer, L3 or main store and L4 or expanded store). Design trade-offs were made to improve processor availability. The processors have been designed to achieve fault tolerant function in power, processor and memory arrays. For example, if one of the power supplies fails, others increase their output to provide full power to the system. Extensive use is made of error detection/correction codes throughout the processor complex. Expanded storage incorporates a sophisticated error correction capability. All double bit errors are corrected, and triple bit errors, are detected.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"IBM ES/9000 system architecture and hardware\",\"authors\":\"W. J. Nohilly, V. Lund\",\"doi\":\"10.1109/ICCD.1991.139968\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A description is given how IBM's Enterprise Systems requirements for data management are implemented in the ES/9000 process series. The ES/9000 processor family is the next step in efficient data movement/management for data that reside anywhere in the Enterprise. To manage this vast amount of data, certain high end ES/9000 models utilize four levels of memory (L1 or first level cache, L2 or second level buffer, L3 or main store and L4 or expanded store). Design trade-offs were made to improve processor availability. The processors have been designed to achieve fault tolerant function in power, processor and memory arrays. For example, if one of the power supplies fails, others increase their output to provide full power to the system. Extensive use is made of error detection/correction codes throughout the processor complex. Expanded storage incorporates a sophisticated error correction capability. All double bit errors are corrected, and triple bit errors, are detected.<<ETX>>\",\"PeriodicalId\":239827,\"journal\":{\"name\":\"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-10-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCD.1991.139968\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCD.1991.139968","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A description is given how IBM's Enterprise Systems requirements for data management are implemented in the ES/9000 process series. The ES/9000 processor family is the next step in efficient data movement/management for data that reside anywhere in the Enterprise. To manage this vast amount of data, certain high end ES/9000 models utilize four levels of memory (L1 or first level cache, L2 or second level buffer, L3 or main store and L4 or expanded store). Design trade-offs were made to improve processor availability. The processors have been designed to achieve fault tolerant function in power, processor and memory arrays. For example, if one of the power supplies fails, others increase their output to provide full power to the system. Extensive use is made of error detection/correction codes throughout the processor complex. Expanded storage incorporates a sophisticated error correction capability. All double bit errors are corrected, and triple bit errors, are detected.<>