Fabrication of Self-Assembled Ni Nanocrystal Flash Memories Using a Polymeric Template

Nanocrystal floating gate (FG) flash memories have attracted a lot of interest due to their potential advantages over conventional flash devices, including scalability and lower operating voltages. In addition, discrete electrically-isolated particles appear to significantly suppress charge loss through lateral paths, which, in turn, gives rise to better retention properties [1]. From a materials standpoint, metal nanocrystals are of interest due to their higher density-of-states and potentially larger work function as compared to Si nanocrystals, which provides a larger retention barrier for stored electrons [2]. The general methods of metal nanocrystal formation include aerosol and self-assembly [3]. However, employing these methods leads to a large fluctuation in both the size and the density of the nanocrystals, which hinders manufacturability and scalability of these devices. In this work, we describe a polymeric self-assembly approach in order to achieve tight control over the size and density of metal nanocrystals using the PS-PMMA diblock copolymer as a nanotemplate. A tri-layer pattern-transfer approach [4] was used to facilitate a metal lift-off process because of the low aspect ratio of the copolymer pattern. The tri-layer structure consists of a PS-b-PMMA copolymer top layer, an SiO2 middle layer, and a polyimide bottom layer. Diblock copolymers are composed of two distinct blocks with high interaction energy. An annealing step tends to promote microphase separation into nanometer-scale polymer domains in order to minimize the total free energy of the system. As a result, a highly uniform, hexagonally-close-packed array ofPMMA cylinders is produced into a PS matrix with size and density specifications that depend on the molecular weight of the copolymer [5]. This polymer-based self-assembly can be easily engineered in terms of the dimension and density of the resulting nanocrystals using copolymers with different molecular weights. In this work, the PMMA removal in glacial acetic acid leaves behind a porous PS template of 20nm-diameter pores with a center-to-center spacing of 40nm. The device fabrication process started with the thermal growth of a 4-nm SiO2 tunnel oxide on a conventional Si wafer. Next, a 60-nm-thick polyimide film was spin-coated onto the substrates, followed by a 15-nm PECVD SiO2. Polyimide was chosen as the bottom layer because of its high glass transition temperature of 309°C, which is higher than the subsequent processing temperatures. The key steps for Ni dot formation using the tri-layer pattern-transfer method are (Fig.1): (a) creating the porous PS template; (b) etching PECVD oxide through the polymer template using CHF3; (c) transferring the oxide patterns into the polyimide film using 02 RIE; (d) nickel deposition through e-beam evaporation; (e) polyimide removal in an organic solvent leaving behind a uniform array of Ni dots. Fig. 2(c) shows the SEM image of the Ni dots with a density of -6 10x ° /cm2. Fabrication of MOS capacitors was completed by depositing a 15 nm LPCVD SiO2 as the control oxide followed by TaN metal gate deposition and patterning (Fig. 3). Interestingly, during the control oxide deposition, Ni nanocrystals agglomerate into smaller dots due to surface-driving forces that minimize the surface free energy (Fig. 2(d)). This effect in turn should improve the Coulomb blockade effect as opposed to the bigger dots. A control sample underwent an identical process as described above, with the exception of Ni deposition. A flat band shift (AVFB) of 0.5V was obtained with a programming voltage of ±8V (Fig. 4). Larger shifts were achieved by applying higher stress pulse voltages (Fig. 5). Longer pulse durations for a certain write voltage (Vw) also led to a wider memory window (Fig. 6). The control sample with no Ni dots exhibits no AVFB, which implies that Ni dots are entirely accountable for the charge-trapping mechanism. We monitored the endurance properties of the memory devices using a write/erase pulse of ±I1 OV, 2ms for up to 2X105 cycles, demonstrating an unchanged memory window (Fig. 7). Fig. 8 shows the retention characteristics of the memory up to 105 s. The extrapolated retention time is higher than 106 s. In summary, a Ni nanocrystal flash memory was demonstrated using a self-assembled polymeric approach providing a tight control over the dimension and density of the nanocrystals. [1] S. Tiwari et al., IEDM Tech. Dig., p. 424, (1995); J. Blauwe et al., IEEE Trans. Nanotechnol., vol. 1, p. 72, (2002). [2] Z. Liu et al., IEEE Trans. Electron Dev., vol. 49, p. 1606, (2002). [3] Y. C. Kang et al., J Aerosol Sci., vol. 26, p. 1131, (1995); Z. Tan et al., Appl. Phys. Lett., vol. 86, 013107, (2005). [4] M. Park et al., J Appl. Phys. Lett., vol. 79, p. 257, (2001). [5] K. W. Guarini et al., IEDM Tech. Dig., p. 541, (2003).