Raffi Der Yeghiayan, Elias Salameh, Mohamad El Mokdad, J. Atallah
{"title":"45纳米CMOS两级锁存比较器","authors":"Raffi Der Yeghiayan, Elias Salameh, Mohamad El Mokdad, J. Atallah","doi":"10.1109/IC2SPM56638.2022.9988906","DOIUrl":null,"url":null,"abstract":"We present a 45nm CMOS high-speed latched comparator suitable for several applications including high-speed data conversion. The comparator is designed and implemented at the schematic level followed by the layout. Detailed corner simulation results are presented. The comparator is able to work with a 5GHz input clock and presents a delay of 51.53ps while consuming 0.551m W of power with an effective area of $\\mathbf{ { 419.52um }}^2$.","PeriodicalId":179072,"journal":{"name":"2022 International Conference on Smart Systems and Power Management (IC2SPM)","volume":"846 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"45nm CMOS Two-Stage Latched Comparator\",\"authors\":\"Raffi Der Yeghiayan, Elias Salameh, Mohamad El Mokdad, J. Atallah\",\"doi\":\"10.1109/IC2SPM56638.2022.9988906\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present a 45nm CMOS high-speed latched comparator suitable for several applications including high-speed data conversion. The comparator is designed and implemented at the schematic level followed by the layout. Detailed corner simulation results are presented. The comparator is able to work with a 5GHz input clock and presents a delay of 51.53ps while consuming 0.551m W of power with an effective area of $\\\\mathbf{ { 419.52um }}^2$.\",\"PeriodicalId\":179072,\"journal\":{\"name\":\"2022 International Conference on Smart Systems and Power Management (IC2SPM)\",\"volume\":\"846 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-11-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 International Conference on Smart Systems and Power Management (IC2SPM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IC2SPM56638.2022.9988906\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 International Conference on Smart Systems and Power Management (IC2SPM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IC2SPM56638.2022.9988906","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
We present a 45nm CMOS high-speed latched comparator suitable for several applications including high-speed data conversion. The comparator is designed and implemented at the schematic level followed by the layout. Detailed corner simulation results are presented. The comparator is able to work with a 5GHz input clock and presents a delay of 51.53ps while consuming 0.551m W of power with an effective area of $\mathbf{ { 419.52um }}^2$.
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