S. Nagaraj, B. Krishna, Botta Chakradhar, Debanjan Sarkar
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引用次数: 1
摘要
由于器件的规模化,半导体器件在性能、速度等方面都有了很大的提高,同时其功耗也一直是人们关注的主要问题之一。随着器件的规模已经达到极限,突破口可能是超大规模集成电路行业的新兴技术,即可逆计算。由于该技术具有零功耗,这是可逆逻辑电路的主要优势。ALU是系统的主要组成部分,主要用于计算机、手机、计算器等应用。采用Verilog硬件描述语言设计32位算术逻辑单元,采用1位ALU实现与逻辑、或逻辑、全阶梯等运算。与不可逆ALU相比,可逆ALU工作速度快。可逆逻辑门降低功耗,延迟和面积。因此,可逆门被用于超大规模集成电路的设计技术中。本文提出了一种采用Toffoli门、Fredkin门和Peres门设计的可逆逻辑门的ALU,它代替了每个位ALU的与或门。所有的逻辑都是使用Modelsim Altera 6.3g软件执行的,合成使用Xilinx ISE 14.7。采用可逆逻辑设计的ALU可减少约34%的面积和48.91%的延迟。
Comparison of 32-bit ALU for Reversible Logic and Irreversible Logic
Semiconductor devices has been undergoing large improvement in terms of performance, speed of the device because of large scaling of devices, simultaneously the power dissipation has been one of the major concern. As the scaling of device has been reached its limits the break through could be the emerging technology i.e., Reversible computing in VLSI industry. As this technology has zero power dissipation, this is a major advantage in the reversible logic circuits. The ALU is major component in the system and it is used in the applications such as computers, mobiles, and calculators. The 32 Bit arithmetic logic unit is designed using Verilog Hardware Description Language with operations such as AND logic, OR logic, FullAdder using One bit ALU. The reversible ALU can work fast as compared with irreversible ALU. Reversible logic gates decreases power dissipation, delay and area. So reversible gates are used in VLSI design techniques. This paper presents an ALU designed of reversible logic gates using Toffoli, Fredkin, and Peres Gate which replaces the AND and OR gate for each one bit ALU. All the logics are performed using the softwares Modelsim Altera 6.3g and the synthesis using Xilinx ISE 14.7. The designed ALU using reversible logic reduces the area about 34% and delay about 48.91%.