软件无线电应用中可重构Delta-Sigma调制器的设计

S. Moallemi, A. Jannesari
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引用次数: 10

摘要

提出了一种提高δ - σ模数转换器(ADC)分辨率的新结构。该技术还显著减小了调制器的面积。此外,前馈拓扑用于降低总功耗。该调制器已在Hspice电路模拟器上以1.8V电源和0.18μm标准CMOS技术进行了仿真。该调制器在GSM和蓝牙标准下的动态范围分别为95.6dB和80dB,功耗分别为4.02mW和4.04mW。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
The design of reconfigurable Delta-Sigma modulator for software defined radio applications
A new architecture for increasing the resolution of Delta-Sigma Analog to Digital Converter (ADC) is presented. The proposed technique also reduced the area of the modulator significantly. Also the feed forward topology is used for reducing the total power consumption. The modulator has been simulated in 0.18μm standard CMOS technology with 1.8V power supply in Hspice circuit simulator. The modulator achieves the Dynamic Range of 95.6dB and 80dB for GSM and Bluetooth standards respectively while consumes 4.02mW and 4.04mW in each case.
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