{"title":"一个多功能和可靠的时钟故障滤波器","authors":"Robert Najvirt, A. Steininger","doi":"10.1109/PATMOS.2015.7347599","DOIUrl":null,"url":null,"abstract":"In today's complex system-on-chip architectures the protection of the clock(s) against glitches introduced by environmental disturbances, attackers, or gating measures is becoming increasingly important. Glitch protection is a delicate issue in the digital domain, as it is inherently coupled with metastability issues. The circuit we propose in this paper outputs a clock that strictly follows an input reference clock in the regular case, but guarantees a minimum output pulse width even in case of arbitrary behavior of the reference. We will give a thorough analysis showing that, unlike most existing solutions, our circuit can handle metastability without any residual risk of upsets. Still its implementation is very simple. Our theoretical claims will be supported by simulation results. Furthermore, we will give some examples on possible use cases for such a circuit, like clock gating, clock self-repair, or defense against clock attacks.","PeriodicalId":325869,"journal":{"name":"2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A versatile and reliable glitch filter for clocks\",\"authors\":\"Robert Najvirt, A. Steininger\",\"doi\":\"10.1109/PATMOS.2015.7347599\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In today's complex system-on-chip architectures the protection of the clock(s) against glitches introduced by environmental disturbances, attackers, or gating measures is becoming increasingly important. Glitch protection is a delicate issue in the digital domain, as it is inherently coupled with metastability issues. The circuit we propose in this paper outputs a clock that strictly follows an input reference clock in the regular case, but guarantees a minimum output pulse width even in case of arbitrary behavior of the reference. We will give a thorough analysis showing that, unlike most existing solutions, our circuit can handle metastability without any residual risk of upsets. Still its implementation is very simple. Our theoretical claims will be supported by simulation results. Furthermore, we will give some examples on possible use cases for such a circuit, like clock gating, clock self-repair, or defense against clock attacks.\",\"PeriodicalId\":325869,\"journal\":{\"name\":\"2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-12-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/PATMOS.2015.7347599\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PATMOS.2015.7347599","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In today's complex system-on-chip architectures the protection of the clock(s) against glitches introduced by environmental disturbances, attackers, or gating measures is becoming increasingly important. Glitch protection is a delicate issue in the digital domain, as it is inherently coupled with metastability issues. The circuit we propose in this paper outputs a clock that strictly follows an input reference clock in the regular case, but guarantees a minimum output pulse width even in case of arbitrary behavior of the reference. We will give a thorough analysis showing that, unlike most existing solutions, our circuit can handle metastability without any residual risk of upsets. Still its implementation is very simple. Our theoretical claims will be supported by simulation results. Furthermore, we will give some examples on possible use cases for such a circuit, like clock gating, clock self-repair, or defense against clock attacks.