一种0.13 μm SiGe BiCMOS中具有>36 dBc谐波抑制的114-126 GHz频率五倍器

2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS) Pub Date : 2019-11-01 DOI:10.1109/BCICTS45179.2019.8972769

Andrea Bilato, V. Issakov, A. Bevilacqua

{"title":"一种0.13 μm SiGe BiCMOS中具有>36 dBc谐波抑制的114-126 GHz频率五倍器","authors":"Andrea Bilato, V. Issakov, A. Bevilacqua","doi":"10.1109/BCICTS45179.2019.8972769","DOIUrl":null,"url":null,"abstract":"This work presents a D-band frequency multiplier by five that shows a harmonic rejection higher than 36 dBc, while consuming only 59 mW from a 1.8 V supply. The fifth harmonic of the 24 GHz input signal is generated by a differential pair driven in hard switching, loaded by a fourth order passive network that filters out the undesired current harmonics. The signal is further amplified by tuned cascode stages to deliver a peak output power of -3.8 dBm. The multiplier is implemented in a 0.13 μm SiGe BiCMOS technology and operates over the 114 to 126 GHz frequency range while occupying a 0.93 × 0.93mm2 silicon area.","PeriodicalId":243314,"journal":{"name":"2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A 114-126 GHz Frequency Quintupler with >36 dBc Harmonic Rejection in 0.13 μm SiGe BiCMOS\",\"authors\":\"Andrea Bilato, V. Issakov, A. Bevilacqua\",\"doi\":\"10.1109/BCICTS45179.2019.8972769\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work presents a D-band frequency multiplier by five that shows a harmonic rejection higher than 36 dBc, while consuming only 59 mW from a 1.8 V supply. The fifth harmonic of the 24 GHz input signal is generated by a differential pair driven in hard switching, loaded by a fourth order passive network that filters out the undesired current harmonics. The signal is further amplified by tuned cascode stages to deliver a peak output power of -3.8 dBm. The multiplier is implemented in a 0.13 μm SiGe BiCMOS technology and operates over the 114 to 126 GHz frequency range while occupying a 0.93 × 0.93mm2 silicon area.\",\"PeriodicalId\":243314,\"journal\":{\"name\":\"2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS)\",\"volume\":\"41 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BCICTS45179.2019.8972769\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BCICTS45179.2019.8972769","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

这项工作提出了一个d波段倍频器，其谐波抑制高于36 dBc，同时从1.8 V电源中仅消耗59 mW。24 GHz输入信号的五次谐波是由硬开关驱动的差分对产生的，由四阶无源网络负载，滤除不需要的电流谐波。信号通过调谐级联码进一步放大，提供-3.8 dBm的峰值输出功率。该乘法器采用0.13 μm SiGe BiCMOS技术，工作频率范围为114至126 GHz，硅面积为0.93 × 0.93mm2。

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A 114-126 GHz Frequency Quintupler with >36 dBc Harmonic Rejection in 0.13 μm SiGe BiCMOS

This work presents a D-band frequency multiplier by five that shows a harmonic rejection higher than 36 dBc, while consuming only 59 mW from a 1.8 V supply. The fifth harmonic of the 24 GHz input signal is generated by a differential pair driven in hard switching, loaded by a fourth order passive network that filters out the undesired current harmonics. The signal is further amplified by tuned cascode stages to deliver a peak output power of -3.8 dBm. The multiplier is implemented in a 0.13 μm SiGe BiCMOS technology and operates over the 114 to 126 GHz frequency range while occupying a 0.93 × 0.93mm2 silicon area.

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2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS)

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