调度和划分ANSI-C程序到多fpga CCM架构

J. Peterson, R. O'Connor, P. Athanas
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引用次数: 45

摘要

现代fpga的尺寸和速度的不断增加,使得一个平均规模的程序的复杂计算,可以在一个小的处理元件集合中执行。有充分的文献证明,在附带的FPGA处理器提供的“虚拟硬件”中执行程序的大部分可以提供比在顺序通用处理器中普通执行更大的加速。不幸的是,目前可用于fpga的开发工具不允许轻松配置多fpga自定义计算机器。FPGA架构的配置需要调度:将计算映射到现有的功能单元。为了利用所有可用的逻辑,计算可能跨越处理元素,要求在一个或多个fpga之间划分子例程。本文提出了一种独立于体系结构的设计工具,用于将用C编写的程序转换为数据流表示,然后有效地调度和划分结果图到多个fpga计算平台上。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Scheduling and partitioning ANSI-C programs onto multi-FPGA CCM architectures
The increasing size and speed of modern FPGAs allow complex computations, on the order of an average sized program, to be performed in a small collection of processing elements. It is well documented that the execution of large sections of a program within the "virtual hardware" offered by an attached FPGA processor can provide substantial speedup over the ordinary execution within a sequential, general-purpose processor. Unfortunately, the development tools currently available for FPGAs do not allow for easily configuring multi-FPGA custom computing machines. Configuration of an FPGA architecture requires scheduling: the mapping of computations onto existing functional units. To take advantage of all available logic, computations may span processing elements, calling for partitioning of a subroutine between one or more FPGAs. In this paper, an architecture-independent design tool is presented for translating programs written in C to a dataflow representation and then efficiently scheduling and partitioning the resulting graphs onto multi-FPGA computing platforms.
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