{"title":"调度和划分ANSI-C程序到多fpga CCM架构","authors":"J. Peterson, R. O'Connor, P. Athanas","doi":"10.1109/FPGA.1996.564821","DOIUrl":null,"url":null,"abstract":"The increasing size and speed of modern FPGAs allow complex computations, on the order of an average sized program, to be performed in a small collection of processing elements. It is well documented that the execution of large sections of a program within the \"virtual hardware\" offered by an attached FPGA processor can provide substantial speedup over the ordinary execution within a sequential, general-purpose processor. Unfortunately, the development tools currently available for FPGAs do not allow for easily configuring multi-FPGA custom computing machines. Configuration of an FPGA architecture requires scheduling: the mapping of computations onto existing functional units. To take advantage of all available logic, computations may span processing elements, calling for partitioning of a subroutine between one or more FPGAs. In this paper, an architecture-independent design tool is presented for translating programs written in C to a dataflow representation and then efficiently scheduling and partitioning the resulting graphs onto multi-FPGA computing platforms.","PeriodicalId":244873,"journal":{"name":"1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines","volume":"182 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"45","resultStr":"{\"title\":\"Scheduling and partitioning ANSI-C programs onto multi-FPGA CCM architectures\",\"authors\":\"J. Peterson, R. O'Connor, P. Athanas\",\"doi\":\"10.1109/FPGA.1996.564821\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The increasing size and speed of modern FPGAs allow complex computations, on the order of an average sized program, to be performed in a small collection of processing elements. It is well documented that the execution of large sections of a program within the \\\"virtual hardware\\\" offered by an attached FPGA processor can provide substantial speedup over the ordinary execution within a sequential, general-purpose processor. Unfortunately, the development tools currently available for FPGAs do not allow for easily configuring multi-FPGA custom computing machines. Configuration of an FPGA architecture requires scheduling: the mapping of computations onto existing functional units. To take advantage of all available logic, computations may span processing elements, calling for partitioning of a subroutine between one or more FPGAs. In this paper, an architecture-independent design tool is presented for translating programs written in C to a dataflow representation and then efficiently scheduling and partitioning the resulting graphs onto multi-FPGA computing platforms.\",\"PeriodicalId\":244873,\"journal\":{\"name\":\"1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines\",\"volume\":\"182 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-04-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"45\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/FPGA.1996.564821\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FPGA.1996.564821","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Scheduling and partitioning ANSI-C programs onto multi-FPGA CCM architectures
The increasing size and speed of modern FPGAs allow complex computations, on the order of an average sized program, to be performed in a small collection of processing elements. It is well documented that the execution of large sections of a program within the "virtual hardware" offered by an attached FPGA processor can provide substantial speedup over the ordinary execution within a sequential, general-purpose processor. Unfortunately, the development tools currently available for FPGAs do not allow for easily configuring multi-FPGA custom computing machines. Configuration of an FPGA architecture requires scheduling: the mapping of computations onto existing functional units. To take advantage of all available logic, computations may span processing elements, calling for partitioning of a subroutine between one or more FPGAs. In this paper, an architecture-independent design tool is presented for translating programs written in C to a dataflow representation and then efficiently scheduling and partitioning the resulting graphs onto multi-FPGA computing platforms.