{"title":"0.5ps 1.4mW 50MS/s奈奎斯特带宽时间放大器基于两步闪存-ΔΣ时间-数字转换器","authors":"Ying Wu, R. Staszewski","doi":"10.1109/EBCCSP.2016.7605282","DOIUrl":null,"url":null,"abstract":"We propose a 50-MS/s two-step flash-ΔΣ time-to-digital converter (TDC) using stable time amplifiers (TAs). The TDC demonstrates low-levels of shaped quantization noise. The system is simulated in 40-nm CMOS and consumes 1.3 mA from a 1.1 V supply. The bandwidth is broadened to Nyquist rate. At frequencies below 25 MHz, the integrated TDC error is as low as 143 fsrms, which is equal to an equivalent TDC resolution of 0.5 ps.","PeriodicalId":411767,"journal":{"name":"2016 Second International Conference on Event-based Control, Communication, and Signal Processing (EBCCSP)","volume":"155 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 0.5ps 1.4mW 50MS/s Nyquist bandwidth time amplifier based two-step flash-ΔΣ time-to-digital converter\",\"authors\":\"Ying Wu, R. Staszewski\",\"doi\":\"10.1109/EBCCSP.2016.7605282\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We propose a 50-MS/s two-step flash-ΔΣ time-to-digital converter (TDC) using stable time amplifiers (TAs). The TDC demonstrates low-levels of shaped quantization noise. The system is simulated in 40-nm CMOS and consumes 1.3 mA from a 1.1 V supply. The bandwidth is broadened to Nyquist rate. At frequencies below 25 MHz, the integrated TDC error is as low as 143 fsrms, which is equal to an equivalent TDC resolution of 0.5 ps.\",\"PeriodicalId\":411767,\"journal\":{\"name\":\"2016 Second International Conference on Event-based Control, Communication, and Signal Processing (EBCCSP)\",\"volume\":\"155 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 Second International Conference on Event-based Control, Communication, and Signal Processing (EBCCSP)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EBCCSP.2016.7605282\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 Second International Conference on Event-based Control, Communication, and Signal Processing (EBCCSP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EBCCSP.2016.7605282","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
摘要
我们提出了一种使用稳定时间放大器(TAs)的50 ms /s两步闪存-ΔΣ时间-数字转换器(TDC)。TDC显示出低水平的形量化噪声。该系统在40纳米CMOS中进行仿真,从1.1 V电源消耗1.3 mA。带宽被加宽到奈奎斯特速率。在低于25 MHz的频率下,集成TDC误差低至143 fsrms,相当于0.5 ps的等效TDC分辨率。
A 0.5ps 1.4mW 50MS/s Nyquist bandwidth time amplifier based two-step flash-ΔΣ time-to-digital converter
We propose a 50-MS/s two-step flash-ΔΣ time-to-digital converter (TDC) using stable time amplifiers (TAs). The TDC demonstrates low-levels of shaped quantization noise. The system is simulated in 40-nm CMOS and consumes 1.3 mA from a 1.1 V supply. The bandwidth is broadened to Nyquist rate. At frequencies below 25 MHz, the integrated TDC error is as low as 143 fsrms, which is equal to an equivalent TDC resolution of 0.5 ps.