LDMOS微处理器紧凑性的改进

2016 IEEE Topical Conference on Power Amplifiers for Wireless and Radio Applications (PAWR) Pub Date : 1900-01-01 DOI:10.1109/PAWR.2016.7440157

Sullivan Plet, G. Bouisse, M. Campovecchio

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引用次数: 0

摘要

本文介绍了一种实现LDMOS mmic输入匹配网络的创新方法，即在有源器件栅极平面而不是50欧姆端口使用集成在输入匹配网络中的非常紧凑的宽带变压器平衡器来实现输入匹配网络。该技术的目的是大幅减少硅的面积，这是由基站市场的紧凑性提高趋势引起的。通过设计一个1.8 GHz到2.2 GHz的MMIC来说明这一点。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Improvement of LDMOS MMICs compactness

This paper describes an innovative mean of realizing input matching networks for LDMOS MMICs, by using a very compact broadband transformer balun, which is integrated in the input matching network, in the active device gate plane instead of the 50 ohms port. The aim of this technique is to significantly reduce the silicon area, which is induced by the base station market trend of compactness improvement. This is illustrated through the design of a 1.8 GHz to 2.2 GHz MMIC.

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来源期刊

2016 IEEE Topical Conference on Power Amplifiers for Wireless and Radio Applications (PAWR)

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