{"title":"统计仓限制:集成电路制造中晶圆位错的方法","authors":"S. Illyés, D. Baglee","doi":"10.1109/ASMC.1990.111228","DOIUrl":null,"url":null,"abstract":"The methodology of selecting and implementing statistical bin limits (SBLs) for wafer-level testing is discussed. Improvements in the manufacturing flow are discussed. It is found that SBLs can detect process shifts, reject misprocessed material, aid in the streamlining of packaged units, and increase the cost effectiveness of these units. It is shown that the methodology does not add to the complexity of the sort flow. Implementation and maintenance are straightforward and simple.<<ETX>>","PeriodicalId":158760,"journal":{"name":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","volume":"522 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Statistical bin limits: an approach to wafer dispositioning in IC fabrication\",\"authors\":\"S. Illyés, D. Baglee\",\"doi\":\"10.1109/ASMC.1990.111228\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The methodology of selecting and implementing statistical bin limits (SBLs) for wafer-level testing is discussed. Improvements in the manufacturing flow are discussed. It is found that SBLs can detect process shifts, reject misprocessed material, aid in the streamlining of packaged units, and increase the cost effectiveness of these units. It is shown that the methodology does not add to the complexity of the sort flow. Implementation and maintenance are straightforward and simple.<<ETX>>\",\"PeriodicalId\":158760,\"journal\":{\"name\":\"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop\",\"volume\":\"522 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-09-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASMC.1990.111228\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASMC.1990.111228","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Statistical bin limits: an approach to wafer dispositioning in IC fabrication
The methodology of selecting and implementing statistical bin limits (SBLs) for wafer-level testing is discussed. Improvements in the manufacturing flow are discussed. It is found that SBLs can detect process shifts, reject misprocessed material, aid in the streamlining of packaged units, and increase the cost effectiveness of these units. It is shown that the methodology does not add to the complexity of the sort flow. Implementation and maintenance are straightforward and simple.<>
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