A fully integrated CMOS GPS receiver with double conversion technique

This paper presents a L1 band low noise integrated global positioning system (GPS) receiver chip using 0.18-um CMOS technology. Dual-conversion with a low-IF architecture was used for this GPS receiver. The receiver is composed of LNA, down-conversion mixers, band pass filter, received signal strength indicator, variable gain amplifier, programmable gain amplifier, ADC, PLL frequency synthesizer and some other key blocks. The receiver exhibits maximum gain of 105dB and noise figure of less than 6dB. The VGA and PGA provide gain control dynamic range over 50dB. The receiver consumes less than 160mW from a 1.8-V supply while occupying a 2.9-mm2 chip area including the ESD I/O pads.