{"title":"一种100ghz宽带分布式解调器","authors":"Zubair Mehmood, M. Seo","doi":"10.1109/ISOCC50952.2020.9332955","DOIUrl":null,"url":null,"abstract":"This paper presents a high speed on-off Keying (OOK) demodulator using distributed approach which is implemented using 28 nm bulk CMOS process. A 100 GHz demodulator post layout full-wave EM simulation results are realized for the data-rate up to 30 Gbps to check the eye diagram at different power levels. The proposed demodulator achieved 50% of eye opening at 30 Gbps for -16 dBm input power. The design consumes 18.5 mW of power and occupies the chip area of 0.135 mm2-,","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A Wideband Distributed Demodulator at 100 GHz\",\"authors\":\"Zubair Mehmood, M. Seo\",\"doi\":\"10.1109/ISOCC50952.2020.9332955\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a high speed on-off Keying (OOK) demodulator using distributed approach which is implemented using 28 nm bulk CMOS process. A 100 GHz demodulator post layout full-wave EM simulation results are realized for the data-rate up to 30 Gbps to check the eye diagram at different power levels. The proposed demodulator achieved 50% of eye opening at 30 Gbps for -16 dBm input power. The design consumes 18.5 mW of power and occupies the chip area of 0.135 mm2-,\",\"PeriodicalId\":270577,\"journal\":{\"name\":\"2020 International SoC Design Conference (ISOCC)\",\"volume\":\"13 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-10-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 International SoC Design Conference (ISOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISOCC50952.2020.9332955\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC50952.2020.9332955","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper presents a high speed on-off Keying (OOK) demodulator using distributed approach which is implemented using 28 nm bulk CMOS process. A 100 GHz demodulator post layout full-wave EM simulation results are realized for the data-rate up to 30 Gbps to check the eye diagram at different power levels. The proposed demodulator achieved 50% of eye opening at 30 Gbps for -16 dBm input power. The design consumes 18.5 mW of power and occupies the chip area of 0.135 mm2-,