{"title":"数字亚阈值操作的设备优化","authors":"B. Paul, K. Roy","doi":"10.1109/DRC.2004.1367809","DOIUrl":null,"url":null,"abstract":"In this paper, we provide optimized transistor structures for digital sub-threshold circuit operation for ultra-low power applications. Results show that at 500 MHz operation, an inverter chain implemented using optimized transistors consumes as low as 2 times less power than circuits using standard transistors and operated in sub-threshold.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Device optimization for digital sub-threshold operation\",\"authors\":\"B. Paul, K. Roy\",\"doi\":\"10.1109/DRC.2004.1367809\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we provide optimized transistor structures for digital sub-threshold circuit operation for ultra-low power applications. Results show that at 500 MHz operation, an inverter chain implemented using optimized transistors consumes as low as 2 times less power than circuits using standard transistors and operated in sub-threshold.\",\"PeriodicalId\":385948,\"journal\":{\"name\":\"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.\",\"volume\":\"31 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-06-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DRC.2004.1367809\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.2004.1367809","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Device optimization for digital sub-threshold operation
In this paper, we provide optimized transistor structures for digital sub-threshold circuit operation for ultra-low power applications. Results show that at 500 MHz operation, an inverter chain implemented using optimized transistors consumes as low as 2 times less power than circuits using standard transistors and operated in sub-threshold.