F. Liu, M. Husain, Z. Li, M. Sotto, D. Burt, J. Fletcher, M. Kataoka, Y. Tsuchiya, S. Saito
{"title":"具有原子平面界面的硅纳米线晶体管的输运特性","authors":"F. Liu, M. Husain, Z. Li, M. Sotto, D. Burt, J. Fletcher, M. Kataoka, Y. Tsuchiya, S. Saito","doi":"10.1109/EDTM.2017.7947561","DOIUrl":null,"url":null,"abstract":"We have fabricated ultra-narrow (sub-10 nm) short channel (100 nm) silicon (Si) nanowire transistors with atomically flat interfaces based on Si-on-Insulator (SOI) substrates. The raised source and drain electrodes were patterned together with the gate electrode. The smaller threshold voltage in the narrower nanowire suggests self-limiting oxidation during the gate oxide formation.","PeriodicalId":280081,"journal":{"name":"2017 IEEE Electron Devices Technology and Manufacturing Conference (EDTM)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Transport properties in silicon nanowire transistors with atomically flat interfaces\",\"authors\":\"F. Liu, M. Husain, Z. Li, M. Sotto, D. Burt, J. Fletcher, M. Kataoka, Y. Tsuchiya, S. Saito\",\"doi\":\"10.1109/EDTM.2017.7947561\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We have fabricated ultra-narrow (sub-10 nm) short channel (100 nm) silicon (Si) nanowire transistors with atomically flat interfaces based on Si-on-Insulator (SOI) substrates. The raised source and drain electrodes were patterned together with the gate electrode. The smaller threshold voltage in the narrower nanowire suggests self-limiting oxidation during the gate oxide formation.\",\"PeriodicalId\":280081,\"journal\":{\"name\":\"2017 IEEE Electron Devices Technology and Manufacturing Conference (EDTM)\",\"volume\":\"32 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE Electron Devices Technology and Manufacturing Conference (EDTM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDTM.2017.7947561\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE Electron Devices Technology and Manufacturing Conference (EDTM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDTM.2017.7947561","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Transport properties in silicon nanowire transistors with atomically flat interfaces
We have fabricated ultra-narrow (sub-10 nm) short channel (100 nm) silicon (Si) nanowire transistors with atomically flat interfaces based on Si-on-Insulator (SOI) substrates. The raised source and drain electrodes were patterned together with the gate electrode. The smaller threshold voltage in the narrower nanowire suggests self-limiting oxidation during the gate oxide formation.