Masahiro Tanaka, Kota Tsurumi, T. Ishii, K. Takeuchi
{"title":"采用标准CMOS工艺和NAND闪存工艺的最佳混合匹配,为1.0V工作NAND闪存提供异质集成程序电压发生器","authors":"Masahiro Tanaka, Kota Tsurumi, T. Ishii, K. Takeuchi","doi":"10.1109/ESSCIRC.2016.7598244","DOIUrl":null,"url":null,"abstract":"For 1.0V operation NAND flash memory, heterogeneously integrated voltage generator is proposed and experimentally demonstrated. The proposed 2-stage boost converter uses high voltage (HV) transistors of standard CMOS process as the 1st stage and HV transistors of NAND flash process as the 2nd stage. The intermediate load capacitance is adaptively adjusted according to the number of NAND flash chips operating simultaneously. As a result, 89% ramp-up time decrease and about 15% chip cost reduction is achieved.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Heterogeneously integrated program voltage generator for 1.0V operation NAND flash with best mix & match of standard CMOS process and NAND flash process\",\"authors\":\"Masahiro Tanaka, Kota Tsurumi, T. Ishii, K. Takeuchi\",\"doi\":\"10.1109/ESSCIRC.2016.7598244\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"For 1.0V operation NAND flash memory, heterogeneously integrated voltage generator is proposed and experimentally demonstrated. The proposed 2-stage boost converter uses high voltage (HV) transistors of standard CMOS process as the 1st stage and HV transistors of NAND flash process as the 2nd stage. The intermediate load capacitance is adaptively adjusted according to the number of NAND flash chips operating simultaneously. As a result, 89% ramp-up time decrease and about 15% chip cost reduction is achieved.\",\"PeriodicalId\":246471,\"journal\":{\"name\":\"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference\",\"volume\":\"36 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2016.7598244\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2016.7598244","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Heterogeneously integrated program voltage generator for 1.0V operation NAND flash with best mix & match of standard CMOS process and NAND flash process
For 1.0V operation NAND flash memory, heterogeneously integrated voltage generator is proposed and experimentally demonstrated. The proposed 2-stage boost converter uses high voltage (HV) transistors of standard CMOS process as the 1st stage and HV transistors of NAND flash process as the 2nd stage. The intermediate load capacitance is adaptively adjusted according to the number of NAND flash chips operating simultaneously. As a result, 89% ramp-up time decrease and about 15% chip cost reduction is achieved.