使用synopsys通用90nm CMOS库的数字VLSI和IC设计课程的全定制设计项目

Eli Lyons, Vish Ganti, R. Goldman, V. Melikyan, H. Mahmoodi
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引用次数: 21

摘要

我们开发了一个基于Synopsys定制设计工具和最近发布的Synopsys 90nm通用库的全定制IC设计流程。所开发的设计流程可用于超大规模集成电路和数字集成电路设计课程的教学。我们还开发了一个全定制设计项目,作为旧金山州立大学“数字VLSI设计”课程的教学项目。该设计项目是在通用的90nm CMOS技术中以完全定制的方式设计一个4位纹波进位加法器,从原理图到布局。开发的设计流程和课程项目提供了一种非常有效的实践方法来教授先进CMOS技术下的数字IC设计和VLSI设计。团队项目以竞赛形式进行,激发了学生的热情和动力,增加了他们的学习经验。竞赛的目的是达到最佳设计质量,即以下设计指标的产物:4位纹波进位加法器的传播延迟、功耗和布局面积。获胜团队的4位加法器延迟为82.2ps,功耗为30.7 μW,版图面积为112.8 μm2。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Full-custom design project for digital VLSI and IC design courses using synopsys generic 90nm CMOS library
We have developed a full-custom IC design flow based on Synopsys custom design tools and the recently released Synopsys 90nm generic library. The developed design flow can be used for teaching VLSI and digital IC design courses. We have also developed a full-custom design project that was used as a course project in teaching “Digital VLSI Design” course at San Francisco State University. The design project is to design a 4-bit ripple carry adder in a full custom fashion from schematic to layout in the generic 90nm CMOS technology. The developed design flow and the course project provide a very effective hands-on approach to teaching digital IC design and VLSI design in advanced CMOS technologies. The team project was conducted in a competition based format providing great enthusiasm and motivation among the students, enhancing their learning experience. The competition was to achieve the best design quality defined as the product of following design metrics: propagation delay, power dissipation, and layout area for the 4-bit ripple carry adder. The winning team achieved a delay of 82.2ps, power dissipation of 30.7 μW, and layout area of 112.8 μm2 for the 4-bit adder.
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