{"title":"随机存储器的在线和离线测试设计","authors":"S. Subramanian, P. Lala","doi":"10.1109/MT.1993.263154","DOIUrl":null,"url":null,"abstract":"The authors propose a testable design of random access memories (RAM) which facilitates both on-line and off-line testing of the devices. The high density of the memory devices necessitates high speed off-line testing techniques. Critical applications desire on-line testability of these devices. The proposed design partitions the chip into blocks and sets in order to achieve high speed off-line testability as well as on-line testability.<<ETX>>","PeriodicalId":248811,"journal":{"name":"Records of the 1993 IEEE International Workshop on Memory Testing","volume":"38 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"On-line and off-line testable design of random access memories\",\"authors\":\"S. Subramanian, P. Lala\",\"doi\":\"10.1109/MT.1993.263154\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The authors propose a testable design of random access memories (RAM) which facilitates both on-line and off-line testing of the devices. The high density of the memory devices necessitates high speed off-line testing techniques. Critical applications desire on-line testability of these devices. The proposed design partitions the chip into blocks and sets in order to achieve high speed off-line testability as well as on-line testability.<<ETX>>\",\"PeriodicalId\":248811,\"journal\":{\"name\":\"Records of the 1993 IEEE International Workshop on Memory Testing\",\"volume\":\"38 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-08-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Records of the 1993 IEEE International Workshop on Memory Testing\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MT.1993.263154\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Records of the 1993 IEEE International Workshop on Memory Testing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MT.1993.263154","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
On-line and off-line testable design of random access memories
The authors propose a testable design of random access memories (RAM) which facilitates both on-line and off-line testing of the devices. The high density of the memory devices necessitates high speed off-line testing techniques. Critical applications desire on-line testability of these devices. The proposed design partitions the chip into blocks and sets in order to achieve high speed off-line testability as well as on-line testability.<>
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