{"title":"基于0.25µm InP DHBT技术的DC-100 GHz带宽和20.5 dB增益限制放大器","authors":"S. Daneshgar, Z. Griffith, M. Rodwell","doi":"10.1109/CSICS.2013.6659197","DOIUrl":null,"url":null,"abstract":"A DC-100 GHz limiting amplifier is designed and fabricated in a 0.25μm InP DHBT technology. The amplifier is designed in two stages using a modified Cherry-Hooper architecture proceeding an emitter-follower at each stage. Consuming 145 mW of power from a -2.5 V supply, it achieves 20.5 dB differential S21 gain with less than 1 dB gain ripple and better than 20 dB and 15 dB input and output return losses, respectively. The group delay of S21 is 9 psec with a variation less than ±5.5 psec around that. Time domain large signal measurements verifies a single-ended output swing of 260 mV.","PeriodicalId":257256,"journal":{"name":"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"A DC-100 GHz Bandwidth and 20.5 dB Gain Limiting Amplifier in 0.25µm InP DHBT Technology\",\"authors\":\"S. Daneshgar, Z. Griffith, M. Rodwell\",\"doi\":\"10.1109/CSICS.2013.6659197\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A DC-100 GHz limiting amplifier is designed and fabricated in a 0.25μm InP DHBT technology. The amplifier is designed in two stages using a modified Cherry-Hooper architecture proceeding an emitter-follower at each stage. Consuming 145 mW of power from a -2.5 V supply, it achieves 20.5 dB differential S21 gain with less than 1 dB gain ripple and better than 20 dB and 15 dB input and output return losses, respectively. The group delay of S21 is 9 psec with a variation less than ±5.5 psec around that. Time domain large signal measurements verifies a single-ended output swing of 260 mV.\",\"PeriodicalId\":257256,\"journal\":{\"name\":\"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-11-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CSICS.2013.6659197\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CSICS.2013.6659197","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A DC-100 GHz Bandwidth and 20.5 dB Gain Limiting Amplifier in 0.25µm InP DHBT Technology
A DC-100 GHz limiting amplifier is designed and fabricated in a 0.25μm InP DHBT technology. The amplifier is designed in two stages using a modified Cherry-Hooper architecture proceeding an emitter-follower at each stage. Consuming 145 mW of power from a -2.5 V supply, it achieves 20.5 dB differential S21 gain with less than 1 dB gain ripple and better than 20 dB and 15 dB input and output return losses, respectively. The group delay of S21 is 9 psec with a variation less than ±5.5 psec around that. Time domain large signal measurements verifies a single-ended output swing of 260 mV.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
