Low power green electronic devices

Summary form only given. The IC chips consume a large amount of energy globally and will continue to increase in the near future. The present IC is a charge-based technology that has logic and memory functions to mimic the human brain. To operate the IC at higher speed, the CMOS inverter of logic IC needs to deliver higher current to charge the capacitors. Thus higher inversion charge (Q_inv) is required in CMOS devices. The conventional method to increase Q_inv in MOSFET is to scale down the gate oxide thickness (t_ox) that also improves the short channel effect. Unfortunately, the scaling t_ox has reached an ultra-thin thickness of ~1.2 nm at 65 nm node CMOS, which causes high gate leakage and DC power (PDC) consumption by direct quantum-mechanical tunneling. Alternatively, higher Q_inv can also be obtained by using high dielectric constant (κ) from fundamental physics of Q=CV. We pioneered the high-κ gate dielectric CMOS starting 1998. Nevertheless, the unwanted high transistor threshold voltage (V_t) is the major challenge. Using unique dipole charge of La₂O₃ and Al₂O₃ high-κ dielectrics, low V_t n- and p-MOSFETs were achieved at 0.6~0.9 nm equivalent-oxide thickness (EOT). Such La₂O₃ and Al₂O₃ high-κ dielectrics have been successfully implemented in 32-nm gate-first CMOS manufacture. To further lower the AC power (P_AC) of CV²/2, we invented the small E_G defect-free Ge-on-Insulator (GOI or GeOI) MOSFET. The 2.5X higher hole mobility and 1.6X better electron mobility were reached in Ge CMOS at 1~1.4 nm EOT that enable the high-performance Ge logic at lower V_d and P_AC. The P_AC can be further lowered down by our initiated 3-dimensional (3D) IC based on the Ge CMOS. Low P_AC non-volatile memory is also required for IC function. Applying high-κ dielectrics into flash memory, fast 100 μs speed and low write voltage of ~10 V were achieved and listed in the Intl. Technology Roadmap for Semiconductors (ITRS). Such high-κ layers can improve the controllability of charge-storage layer and realize simpler planar structure. At present, the high-κ flash memory has been successfully implemented at 20 nm 128 Gb array manufacture. These high-κ CMOS and flash memory realize the low power green electronic devices.