{"title":"RFID低功耗915MHz CMOS LNA设计优化技术","authors":"Xiushan Wu, Ling Sun, Zhigong Wang","doi":"10.1109/ICMMT.2007.381397","DOIUrl":null,"url":null,"abstract":"According to the definition of noise figure, this paper presents a detailed analysis of the noise parameter of a low noise amplified (LNA) in a CMOS cascode topology with the source degeneration inductance and gate shunt capacitance. Based on the derived equations, the important application of this topology is discussed and a low power UHF CMOS LNA is optimized for RFID. The simulated results show a noise figure of 0.7dB, a power gain of 12.5dB, and an IIP3 of -4dBm while dissipating 2.1mA from a 1.8V supply. As a result, very low noise figures become possible already at very low power consumption levels.","PeriodicalId":409971,"journal":{"name":"2007 International Conference on Microwave and Millimeter Wave Technology","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Low-Power 915MHz CMOS LNA Design Optimization Techniques for RFID\",\"authors\":\"Xiushan Wu, Ling Sun, Zhigong Wang\",\"doi\":\"10.1109/ICMMT.2007.381397\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"According to the definition of noise figure, this paper presents a detailed analysis of the noise parameter of a low noise amplified (LNA) in a CMOS cascode topology with the source degeneration inductance and gate shunt capacitance. Based on the derived equations, the important application of this topology is discussed and a low power UHF CMOS LNA is optimized for RFID. The simulated results show a noise figure of 0.7dB, a power gain of 12.5dB, and an IIP3 of -4dBm while dissipating 2.1mA from a 1.8V supply. As a result, very low noise figures become possible already at very low power consumption levels.\",\"PeriodicalId\":409971,\"journal\":{\"name\":\"2007 International Conference on Microwave and Millimeter Wave Technology\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-04-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 International Conference on Microwave and Millimeter Wave Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICMMT.2007.381397\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 International Conference on Microwave and Millimeter Wave Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMMT.2007.381397","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Low-Power 915MHz CMOS LNA Design Optimization Techniques for RFID
According to the definition of noise figure, this paper presents a detailed analysis of the noise parameter of a low noise amplified (LNA) in a CMOS cascode topology with the source degeneration inductance and gate shunt capacitance. Based on the derived equations, the important application of this topology is discussed and a low power UHF CMOS LNA is optimized for RFID. The simulated results show a noise figure of 0.7dB, a power gain of 12.5dB, and an IIP3 of -4dBm while dissipating 2.1mA from a 1.8V supply. As a result, very low noise figures become possible already at very low power consumption levels.
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