{"title":"基于原始操作分析的CPU性能建模","authors":"V. K, M. Purnaprajna","doi":"10.1109/SPIN48934.2020.9070898","DOIUrl":null,"url":null,"abstract":"Modern multi-core processors are complex because of their complicated memory hierarchies, superscalar issue of instructions, pipeline architecture, out-of-order execution and speculative execution due to branches in the program code. These features of the CPU are beneficial to improve the application performance. These processors have to be modelled to arrive at the trade-offs of design decisions such as power, time, throughput and latency. Modeling these complex micro-architectures is a very challenging task. In this work, we present a simple CPU modeling technique for data-parallel applications based on minimum offline profiling information and detailed static code analysis. This model, first identifies the primitive operations of the application kernels and then, based on the available offline profiled information, it estimates the performance of the given application kernel using either a SUM model or a MAX model. Experimental results show that an average estimation error of 7.19% and 41.4% is seen across data-parallel benchmarks from the Polybench suite for large and small problem sizes respectively on a multi-core CPU architecture.","PeriodicalId":126759,"journal":{"name":"2020 7th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"4 5","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"CPU Performance Modeling through Analysis of Primitive Operations\",\"authors\":\"V. K, M. Purnaprajna\",\"doi\":\"10.1109/SPIN48934.2020.9070898\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Modern multi-core processors are complex because of their complicated memory hierarchies, superscalar issue of instructions, pipeline architecture, out-of-order execution and speculative execution due to branches in the program code. These features of the CPU are beneficial to improve the application performance. These processors have to be modelled to arrive at the trade-offs of design decisions such as power, time, throughput and latency. Modeling these complex micro-architectures is a very challenging task. In this work, we present a simple CPU modeling technique for data-parallel applications based on minimum offline profiling information and detailed static code analysis. This model, first identifies the primitive operations of the application kernels and then, based on the available offline profiled information, it estimates the performance of the given application kernel using either a SUM model or a MAX model. Experimental results show that an average estimation error of 7.19% and 41.4% is seen across data-parallel benchmarks from the Polybench suite for large and small problem sizes respectively on a multi-core CPU architecture.\",\"PeriodicalId\":126759,\"journal\":{\"name\":\"2020 7th International Conference on Signal Processing and Integrated Networks (SPIN)\",\"volume\":\"4 5\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-02-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 7th International Conference on Signal Processing and Integrated Networks (SPIN)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SPIN48934.2020.9070898\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 7th International Conference on Signal Processing and Integrated Networks (SPIN)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SPIN48934.2020.9070898","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
CPU Performance Modeling through Analysis of Primitive Operations
Modern multi-core processors are complex because of their complicated memory hierarchies, superscalar issue of instructions, pipeline architecture, out-of-order execution and speculative execution due to branches in the program code. These features of the CPU are beneficial to improve the application performance. These processors have to be modelled to arrive at the trade-offs of design decisions such as power, time, throughput and latency. Modeling these complex micro-architectures is a very challenging task. In this work, we present a simple CPU modeling technique for data-parallel applications based on minimum offline profiling information and detailed static code analysis. This model, first identifies the primitive operations of the application kernels and then, based on the available offline profiled information, it estimates the performance of the given application kernel using either a SUM model or a MAX model. Experimental results show that an average estimation error of 7.19% and 41.4% is seen across data-parallel benchmarks from the Polybench suite for large and small problem sizes respectively on a multi-core CPU architecture.