Low Power High Stability SRAM Cell with Combined Effect of Sleep- Stack and Diode Gated Technique

In this work, Static Random Access Memory (SRAM) is designed on 0.18 micron by using CADENCE virtuoso tools. It focuses on the power consumption and leakage power improvement since SRAM has high leakage power consumption. Leakage power and performance of SRAM cell is greatly affected by the development of technology and speed of operation. The total leakage power is greatly affected by the combined effect of subthreshold leakage current and gate leakage current. With the fall of oxide thickness the gate leakage current increases exponentially. Hence efficient techniques are required which will address the gate leakage component. In our design, with sleep- stack two more transistors are used in conventional SRAM cell to minimize the gate leakage current and to improve the performance of the memory cell.