有效的片上通信数据流ip

Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004. Pub Date : 2004-09-27 DOI:10.1109/ASAP.2004.10036

A. Fraboulet, T. Risset

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引用次数: 11

摘要

我们解释了一种将数据流硬件加速器(IP)集成到片上系统中的系统方法。对数据流IP的通信行为进行了抽象，为接口生成提供了基础。我们还解释了该接口生成器必须考虑的参数。我们通过对集成数据流IP的SoC进行周期精确的位精确仿真来验证我们的接口机制。

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Efficient on-chip communications for data-flow IPs

We explain a systematic way of interfacing data-flow hardware accelerators (IP) for their integration in a system on chip. We abstract the communication behaviour of the data flow IP so as to provide basis for an interface generator. We also explain which parameter this interface generator has to take into account. We validate our interface mechanism by a cycle accurate bit accurate simulation of a SoC integrating a data-flow IP.

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来源期刊

Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004.

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