VHDL设计自动化和数据建模

Proceedings of TENCON '93. IEEE Region 10 International Conference on Computers, Communications and Automation Pub Date : 1993-10-19 DOI:10.1109/TENCON.1993.320057

Tian Zhong, Shen Yongchao

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摘要

本文提出了一个高级的、集成的、面向仿真的VHDL设计自动化环境。VHDL数据建模是解决设计自动化系统中大量数据管理问题的核心，也是实现系统集成的关键。提出了一种VHDL的中间表示格式和一种适合VHDL语义的内部数据模型，用于VLSI电路的建模和仿真

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VHDL design automation and data modeling

This paper presents a high-level, integrated, simulation-oriented design automation environment for VHDL. Much emphasis is placed on VHDL data modeling, which is central to solving the large problem of data management for design automation systems and is a key to system integration. An intermediate representation format of VHDL, and an inner data model that is suitable for the VHDL semantics are proposed for modeling and simulating VLSI circuits.<>

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Proceedings of TENCON '93. IEEE Region 10 International Conference on Computers, Communications and Automation

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