探索在SoC芯片中嵌入微处理器核心的多个集成电路

Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434) Pub Date : 2000-08-28 DOI:10.1109/APASIC.2000.896970

Ing-Jer Huang, Chung-Fu Kao

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引用次数: 3

摘要

本文探讨了将嵌入式电路仿真集成到具有多个微处理器(微控制器)内核的SoC(片上系统)芯片中的架构替代方案。备选方案包括分布式、集中式和分层样式。分析了这些替代方案的优缺点。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Exploration of multiple ICEs for embedded microprocessor cores in an SoC chip

This paper explores architectural alternatives in the integration of embedded in-circuit emulation into a SoC (System-on-Chip) chip with multiple microprocessor (microcontroller) cores. The alternatives include distributed, centralized and hierarchical styles. Advantages and disadvantages of these alternatives are analyzed.

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Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)

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