低功耗256kb SRAM设计

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI:10.1109/ICVD.1999.745126

B. Bhaumik, Pravas Pradhan, G. Visweswaran, Rajamohan Varambally, Anand Hardi

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引用次数: 6

摘要

本文提出了一种低功耗SRAM的设计方案。研究了SGS Thomson中使用的现有SRAM架构，以探索降低各种块功耗的可能性。采用分字线(DWL)方案。特别强调了降低解码器的功耗。在原理图仿真中引入了一种新的关键路径模型。这大大降低了模拟时间。仿真结果证实了该方法的有效性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A low power 256 KB SRAM design

In this paper a low power SRAM design is presented. Existing SRAM architectures used in SGS Thomson were studied to explore the possibilities in bringing down power dissipation in various blocks. A Divided word line (DWL) scheme was implemented. Particular emphasis was put to reduce power consumption in decoders. A new critical path model was introduced for schematic simulation. This lowered the simulation time considerably. Simulation results confirmed the effectiveness of our approach.

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Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)

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