55nm CMOS 12位250MHz数模转换器，采用动态电压缩放(DVS)技术，通过单电感双输出(SIDO)转换器

2011 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2011-10-13 DOI:10.1109/ESSCIRC.2011.6044987

Tzu-Chi Huang, W. Chou, Yu-Huei Lee, Yao-Yi Yang, Ke-Horng Chen, Y. Peng, F. Hsueh

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引用次数: 3

摘要

这款55nm CMOS 12位电流转向DAC直接由单电感双输出(SIDO)开关DC-DC转换器和动态电压缩放(DVS)技术供电，将DAC的功率效率提高了25%，SFDR达到65.34dB。提出的3S方法，包括分离、分裂和移位，有效地将电流失配降低到0.2%以内，并抑制了SIDO转换器的开关噪声干扰。与传统方法相比，12位DAC和SIDO模块实现了兼容的性能，并且具有面积和能源效率的优点。

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55nm CMOS 12-bit 250MHz digital-to-analog converter with dynamic voltage scaling (DVS) technique through single-inductor dual-output (SIDO) converter

This 55nm CMOS 12-bit current-steering DAC directly powered by the single-inductor dual-output (SIDO) switching DC-DC converter with the dynamic voltage scaling (DVS) technique improves the DAC's power efficiency by 25% and achieves 65.34dB SFDR. The proposed 3S method, including separating, splitting, and shifting, effectively reduces the current mismatching within 0.2% and suppresses the switching noise interference from the SIDO converter. The 12-bit DAC and SIDO module achieve compatible performance compare to the tradition method and has the benefit of area and energy efficiency.

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2011 Proceedings of the ESSCIRC (ESSCIRC)

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