Differential Input Area Efficient Current Comparator

Differential input area efficient current comparator for multichannel detector (sensor) applications is presented. Comparator consists of current preamplifier, hysteresis latch, amplifier-voltage limiter and output low-voltage to CMOS translator, having built-in polarity selection switch. The latch geometry was chosen to feature non-zero hysteresis and minimum size. The key features of the proposed solution are low voltage swing before translator, low power consumption and simplicity. The comparator was developed in UMC 180 nm MMRF CMOS process. The power consumption is in range of $60\ \mu \mathrm{W}$ at 1.8 V for all PVT variations. Its layout cell was designed to be an area efficient one and occupies $1200\ \mu \mathrm{m}^{2}$.