{"title":"大规模集成电路中砷化镓逻辑门的性能","authors":"P. Solomon","doi":"10.1109/IEDM.1978.189387","DOIUrl":null,"url":null,"abstract":"This paper examines the theoretical performance of GaAs MESFET logic gates and attempts to obtain a realistic comparison of GaAs vs Si devices under typical loading conditions imposed by large random logic arrays. GaAs was found to have a speed advantage of 3-6 over Si, depending on the operating voltage. Normally off type MESFET devices were attractive at gate lengths of 0.5µm, giving loaded delays of 105ps. Logic swings were 600mV requiring a threshold voltage control of ±50mV.","PeriodicalId":164556,"journal":{"name":"1978 International Electron Devices Meeting","volume":"72 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"The performance of GaAs logic gates in LSI\",\"authors\":\"P. Solomon\",\"doi\":\"10.1109/IEDM.1978.189387\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper examines the theoretical performance of GaAs MESFET logic gates and attempts to obtain a realistic comparison of GaAs vs Si devices under typical loading conditions imposed by large random logic arrays. GaAs was found to have a speed advantage of 3-6 over Si, depending on the operating voltage. Normally off type MESFET devices were attractive at gate lengths of 0.5µm, giving loaded delays of 105ps. Logic swings were 600mV requiring a threshold voltage control of ±50mV.\",\"PeriodicalId\":164556,\"journal\":{\"name\":\"1978 International Electron Devices Meeting\",\"volume\":\"72 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1978 International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.1978.189387\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1978 International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.1978.189387","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper examines the theoretical performance of GaAs MESFET logic gates and attempts to obtain a realistic comparison of GaAs vs Si devices under typical loading conditions imposed by large random logic arrays. GaAs was found to have a speed advantage of 3-6 over Si, depending on the operating voltage. Normally off type MESFET devices were attractive at gate lengths of 0.5µm, giving loaded delays of 105ps. Logic swings were 600mV requiring a threshold voltage control of ±50mV.