Pieter A. J. Nuyts, P. Singerl, F. Dielacher, P. Reynaert, W. Dehaene
{"title":"基于全数字延迟线的65纳米CMOS ghz范围多模发射机前端","authors":"Pieter A. J. Nuyts, P. Singerl, F. Dielacher, P. Reynaert, W. Dehaene","doi":"10.1109/ESSCIRC.2011.6044990","DOIUrl":null,"url":null,"abstract":"A fully digital up-converter for wireless transmission in the GHz range is presented. The system consists of a polar modulator which uses PWM for the amplitude modulator (AM). Phase modulation (PM) is implemented by shifting the carrier in time. Both the PWM and the PM are implemented using asynchronous delay lines which allow time resolutions down to 10 ps without the need for high-frequent clock signals. The system is designed to drive two class-E power amplifiers with a power combiner. It supports a continuous range of carrier frequencies starting at 946 MHz and limited upwards only by the desired resolution. The modulator has been implemented in 65-nm CMOS. Results show error vector magnitude (EVM) values between 1.24% (−38.1 dB) at 946 MHz and 3.98% (−28.0 dB) at 2.4 GHz for 64-QAM OFDM signals.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"40","resultStr":"{\"title\":\"A fully digital delay-line based GHz-range multimode transmitter front-end in 65-nm CMOS\",\"authors\":\"Pieter A. J. Nuyts, P. Singerl, F. Dielacher, P. Reynaert, W. Dehaene\",\"doi\":\"10.1109/ESSCIRC.2011.6044990\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A fully digital up-converter for wireless transmission in the GHz range is presented. The system consists of a polar modulator which uses PWM for the amplitude modulator (AM). Phase modulation (PM) is implemented by shifting the carrier in time. Both the PWM and the PM are implemented using asynchronous delay lines which allow time resolutions down to 10 ps without the need for high-frequent clock signals. The system is designed to drive two class-E power amplifiers with a power combiner. It supports a continuous range of carrier frequencies starting at 946 MHz and limited upwards only by the desired resolution. The modulator has been implemented in 65-nm CMOS. Results show error vector magnitude (EVM) values between 1.24% (−38.1 dB) at 946 MHz and 3.98% (−28.0 dB) at 2.4 GHz for 64-QAM OFDM signals.\",\"PeriodicalId\":239979,\"journal\":{\"name\":\"2011 Proceedings of the ESSCIRC (ESSCIRC)\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-10-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"40\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 Proceedings of the ESSCIRC (ESSCIRC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2011.6044990\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 Proceedings of the ESSCIRC (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2011.6044990","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A fully digital delay-line based GHz-range multimode transmitter front-end in 65-nm CMOS
A fully digital up-converter for wireless transmission in the GHz range is presented. The system consists of a polar modulator which uses PWM for the amplitude modulator (AM). Phase modulation (PM) is implemented by shifting the carrier in time. Both the PWM and the PM are implemented using asynchronous delay lines which allow time resolutions down to 10 ps without the need for high-frequent clock signals. The system is designed to drive two class-E power amplifiers with a power combiner. It supports a continuous range of carrier frequencies starting at 946 MHz and limited upwards only by the desired resolution. The modulator has been implemented in 65-nm CMOS. Results show error vector magnitude (EVM) values between 1.24% (−38.1 dB) at 946 MHz and 3.98% (−28.0 dB) at 2.4 GHz for 64-QAM OFDM signals.
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