{"title":"用于多芯片模块的无磁倒装芯片","authors":"J. Goldstein, E. A. Logan, B.S. Femandez","doi":"10.1109/MCMC.1996.510766","DOIUrl":null,"url":null,"abstract":"The no-flux, Utilitarian Solder System (\"No-FUSS\") flip-chip process is a versatile technique that can be used with virtually any die. The process combines Au ball bumping of the die with Pb/Sn-indium electroplating of the substrate. Previous work demonstrated that substrates electroplated with an 8 /spl mu/m indium cap over 16 /spl mu/m of 95Pb/5Sn had shown consistently reliable interconnects after thermal shock and thermal aging testing. Preliminary evaluations of samples with only 2 /spl mu/m of indium over 22 /spl mu/m of 95Pb/5Sn had shown promising results from a metallurgical viewpoint and further work was recommended. The current study compares the reliability and reproducibility of flip-chip interconnects prepared with a 2 /spl mu/m indium cap with previous data from 8 /spl mu/m samples. The results indicate that, although it is possible to produce low resistance, reliable interconnect using a 2 /spl mu/m indium layer, the process is nor yet as reproducible as the 8 /spl mu/m process and requires further development before it can be fully utilized.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Fluxless flip-chip for multichip modules\",\"authors\":\"J. Goldstein, E. A. Logan, B.S. Femandez\",\"doi\":\"10.1109/MCMC.1996.510766\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The no-flux, Utilitarian Solder System (\\\"No-FUSS\\\") flip-chip process is a versatile technique that can be used with virtually any die. The process combines Au ball bumping of the die with Pb/Sn-indium electroplating of the substrate. Previous work demonstrated that substrates electroplated with an 8 /spl mu/m indium cap over 16 /spl mu/m of 95Pb/5Sn had shown consistently reliable interconnects after thermal shock and thermal aging testing. Preliminary evaluations of samples with only 2 /spl mu/m of indium over 22 /spl mu/m of 95Pb/5Sn had shown promising results from a metallurgical viewpoint and further work was recommended. The current study compares the reliability and reproducibility of flip-chip interconnects prepared with a 2 /spl mu/m indium cap with previous data from 8 /spl mu/m samples. The results indicate that, although it is possible to produce low resistance, reliable interconnect using a 2 /spl mu/m indium layer, the process is nor yet as reproducible as the 8 /spl mu/m process and requires further development before it can be fully utilized.\",\"PeriodicalId\":126969,\"journal\":{\"name\":\"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)\",\"volume\":\"34 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-02-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MCMC.1996.510766\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MCMC.1996.510766","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The no-flux, Utilitarian Solder System ("No-FUSS") flip-chip process is a versatile technique that can be used with virtually any die. The process combines Au ball bumping of the die with Pb/Sn-indium electroplating of the substrate. Previous work demonstrated that substrates electroplated with an 8 /spl mu/m indium cap over 16 /spl mu/m of 95Pb/5Sn had shown consistently reliable interconnects after thermal shock and thermal aging testing. Preliminary evaluations of samples with only 2 /spl mu/m of indium over 22 /spl mu/m of 95Pb/5Sn had shown promising results from a metallurgical viewpoint and further work was recommended. The current study compares the reliability and reproducibility of flip-chip interconnects prepared with a 2 /spl mu/m indium cap with previous data from 8 /spl mu/m samples. The results indicate that, although it is possible to produce low resistance, reliable interconnect using a 2 /spl mu/m indium layer, the process is nor yet as reproducible as the 8 /spl mu/m process and requires further development before it can be fully utilized.