基于FPGA的双冗余容错CAN控制器

V. Jacintha, K.H. Shakthimuruzan, V. Kripakaran, S. Lokeshwaran
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引用次数: 2

摘要

摘要/ abstract摘要:CAN (Controller Area Network,控制器区域网络)是目前发展最为突出的数据总线之一,具有抗干扰能力强、成本低、维护方便等特点。因此,本文提出了一种基于FPGA芯片的双冗余can总线控制器(DRCC)。以往的双冗余can总线的实现方法仅依靠软件实现,存在可靠性问题和实时性差等缺点。因此,本文成功地提出了一种基于硬件的冗余管理单元,该单元是基于CAN规范2.0版本的错误处理规则开发的。提出了一种基于FPGA的多核冗余can总线控制器(DRCC)。该设计被纳入Altera Cyclone II芯片用于测试目的,并证实该设计满足高现实成就和可靠性所需的要求,并具有未来几年的新兴趋势。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
FPGA Based Dual Redundancy CAN Controller with Fault Tolerance
Ahstract- CAN (Controller Area Network) has emerged to be one among the most prominent data bus which has the following features, which are anti-interference capability, reduced cost as well as ease of maintenance. Hence in this paper we propose, a Dual Redundancy CAN-bus Controller (DRCC) rooted strongly on FPGA chip. Earlier the method for dual redundancy CAN-bus is accomplished only with the help of software, which obviously has the following disadvantages such as reliability issues and meager real-time performance. Hence, a hardware based redundancy management unit is successfully brought forth in this paper, which is developed on the error handling rule with a CAN specification version of 2.0. A multicore redundant FPGA based CAN-bus Controller (DRCC) is developed. The design is incorporated into a Altera Cyclone II chip for testing purpose and it is confirmed that the design meets the requirement needed for high realistic achievement and dependability, with emerging trends for the forthcoming years.
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